All display 9 and display 10 platforms has only 4 bits for the memory
frequency but display 11 platforms it changes to 8 bits.
Display 9 platforms has another register in bits 7:4 that prevents us
to have a single mask.
Also adding new mask with the current name in CRWebViewer, not
sure why current mask is named like this.
Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dram.c | 7 +++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c3..041f7dc9e0d94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11148,6 +11148,7 @@ enum skl_power_gate {
#define SKL_MEMORY_FREQ_MULTIPLIER_HZ 266666666
#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU _MMIO(MCHBAR_MIRROR_BASE_SNB +
0x5E04)
#define SKL_REQ_DATA_MASK (0xF << 0)
+#define ICL_FREQ_MASK (0xFF << 0)
#define DG1_GEAR_TYPE REG_BIT(16)
#define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB
+ 0x5000)
diff --git a/drivers/gpu/drm/i915/intel_dram.c
b/drivers/gpu/drm/i915/intel_dram.c
index 30a0cab5eff46..558589b1202d6 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -257,8 +257,11 @@ skl_get_dram_info(struct drm_i915_private *i915)
val = intel_uncore_read(&i915->uncore,
SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
- mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
- SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
+ if (DISPLAY_VER(i915) == 11)
+ val &= ICL_FREQ_MASK;
+ else
+ val &= SKL_REQ_DATA_MASK;
+ mem_freq_khz = DIV_ROUND_UP(val * SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
if (dram_info->num_channels * mem_freq_khz == 0) {
drm_info(&i915->drm,
--
2.33.0
