On Fri, 2021-11-05 at 17:37 -0700, Radhakrishna Sripada wrote:
> The earlier update to BW formulae broke ADL-P. Include
> GEN13 to use TGL path for BW parameters.
include display 13.
With that:
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Fixes: c64a9a7c05be drm/i915: Update memory bandwidth formulae
> Cc: Matt Roper <matthew.d.ro...@intel.com>
> Reported-by: José Roberto de Souza <jose.so...@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 15c006194c85..abec394f6869 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -147,7 +147,7 @@ static int icl_get_qgv_points(struct drm_i915_private
> *dev_priv,
> qi->num_points = dram_info->num_qgv_points;
> qi->num_psf_points = dram_info->num_psf_gv_points;
>
> - if (DISPLAY_VER(dev_priv) == 12)
> + if (DISPLAY_VER(dev_priv) >= 12)
> switch (dram_info->type) {
> case INTEL_DRAM_DDR4:
> qi->t_bl = is_y_tile ? 8 : 4;
