On Wed, 2021-12-01 at 17:25 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> There's no need to have separate masks for the stride bitfield
> in PLANE_STRIDE for different platforms. All the extra bits
> are hardcoded to zero anyway.
>
> Also the masks we're using now don't even match the actual hardware
> since the bitfield was only 10 bits on skl/derivatives, only getting
> bumped to 11 bits on glk.
>
> So let's just use a 12 bit mask for everything.
Reviewed-by: José Roberto de Souza <jose.so...@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +----
> drivers/gpu/drm/i915/i915_reg.h | 3 +--
> 2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 09948922016b..984bb35ecf06 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2347,10 +2347,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
> stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
>
> - if (DISPLAY_VER(dev_priv) >= 13)
> - fb->pitches[0] = (val & PLANE_STRIDE_MASK_XELPD) * stride_mult;
> - else
> - fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
> + fb->pitches[0] = (val & PLANE_STRIDE_MASK) * stride_mult;
>
> aligned_height = intel_fb_align_height(fb, 0, fb->height);
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 02d8db03c0bf..6066b1e2763c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7440,8 +7440,7 @@ enum {
> _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B)
> #define PLANE_STRIDE(pipe, plane) \
> _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe))
> -#define PLANE_STRIDE_MASK REG_GENMASK(10, 0)
> -#define PLANE_STRIDE_MASK_XELPD REG_GENMASK(11, 0)
> +#define PLANE_STRIDE_MASK REG_GENMASK(11, 0)
>
> #define _PLANE_POS_1_B 0x7118c
> #define _PLANE_POS_2_B 0x7128c
