On Wed, 09 Feb 2022, Ville Syrjala <ville.syrj...@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> IPS must be disabled prior to disabling the last plane (excluding
> the cursor). Make the code do that instead of assuming the primary
> plane would be the last one. This is probably 100% theoretical
> as the BIOS should never light up the other planes anyway. But
> no harm in making the code totally consistent.
>
> Also let's update the ips_enabled flag in the crtc state afterwards
> so that the first atomic commit has accurate information about
> the state of IPS.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
I admit, didn't have the time to dig into the details here now, so let's
just say, seems reasonable,
Acked-by: Jani Nikula <jani.nik...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index cdfee4ba1166..401a339973bf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -753,9 +753,11 @@ void intel_plane_disable_noatomic(struct intel_crtc
> *crtc,
> crtc_state->data_rate[plane->id] = 0;
> crtc_state->min_cdclk[plane->id] = 0;
>
> - if (plane->id == PLANE_PRIMARY &&
> - hsw_ips_disable(crtc_state))
> + if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
> + hsw_ips_disable(crtc_state)) {
> + crtc_state->ips_enabled = false;
> intel_crtc_wait_for_next_vblank(crtc);
> + }
>
> /*
> * Vblank time updates from the shadow to live plane control register
--
Jani Nikula, Intel Open Source Graphics Center
