The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to all later platforms), align the power domain names with the spec.
Signed-off-by: Imre Deak <imre.d...@intel.com> Reviewed-by: Jouni Högander <jouni.hogan...@intel.com> --- .../gpu/drm/i915/display/intel_display_power.c | 10 +--------- .../gpu/drm/i915/display/intel_display_power.h | 4 ---- .../drm/i915/display/intel_display_power_map.c | 16 ++++++++-------- 3 files changed, 9 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index f1f4d877a9751..8b7b7a87df03e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -166,14 +166,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain) return "AUX_E_XELPD"; case POWER_DOMAIN_AUX_IO_A: return "AUX_IO_A"; - case POWER_DOMAIN_AUX_TBT_C: - return "AUX_TBT_C"; - case POWER_DOMAIN_AUX_TBT_D: - return "AUX_TBT_D"; - case POWER_DOMAIN_AUX_TBT_E: - return "AUX_TBT_E"; - case POWER_DOMAIN_AUX_TBT_F: - return "AUX_TBT_F"; case POWER_DOMAIN_AUX_TBT1: return "AUX_TBT1"; case POWER_DOMAIN_AUX_TBT2: @@ -2341,7 +2333,7 @@ d11_port_domains[] = { .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C, .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C, .aux_legacy_usbc = POWER_DOMAIN_AUX_C, - .aux_tbt = POWER_DOMAIN_AUX_TBT_C, + .aux_tbt = POWER_DOMAIN_AUX_TBT1, }, }; diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h index b58c5bada6d85..e04b2ff7b4b99 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.h +++ b/drivers/gpu/drm/i915/display/intel_display_power.h @@ -100,10 +100,6 @@ enum intel_display_power_domain { POWER_DOMAIN_AUX_E_XELPD, POWER_DOMAIN_AUX_IO_A, - POWER_DOMAIN_AUX_TBT_C, - POWER_DOMAIN_AUX_TBT_D, - POWER_DOMAIN_AUX_TBT_E, - POWER_DOMAIN_AUX_TBT_F, POWER_DOMAIN_AUX_TBT1, POWER_DOMAIN_AUX_TBT2, diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 86d937f8bfe13..d9cf3d3bc02e7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -622,10 +622,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4, POWER_DOMAIN_AUX_D, \ POWER_DOMAIN_AUX_E, \ POWER_DOMAIN_AUX_F, \ - POWER_DOMAIN_AUX_TBT_C, \ - POWER_DOMAIN_AUX_TBT_D, \ - POWER_DOMAIN_AUX_TBT_E, \ - POWER_DOMAIN_AUX_TBT_F + POWER_DOMAIN_AUX_TBT1, \ + POWER_DOMAIN_AUX_TBT2, \ + POWER_DOMAIN_AUX_TBT3, \ + POWER_DOMAIN_AUX_TBT4 I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3, ICL_PW_3_POWER_DOMAINS, @@ -668,10 +668,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E); I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E); -I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3); +I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4); static const struct i915_power_well_desc icl_power_wells_pw_1[] = { { -- 2.30.2