[Intel-gfx] [PATCH v2] drm/i915/dg2: Add workaround 22014600077

[Swathi Dhanavanthri]

Signed-off-by: Swathi Dhanavanthri <swathi.dhanavant...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 98ede9c93f00..2063c8758934 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1068,6 +1068,7 @@
 #define   GEN9_ENABLE_GPGPU_PREEMPTION         REG_BIT(2)
 
 #define GEN10_CACHE_MODE_SS                    _MMIO(0xe420)
+#define   ENABLE_EU_COUNT_FOR_TDL_FLUSH                REG_BIT(10)
 #define   ENABLE_PREFETCH_INTO_IC              REG_BIT(3)
 #define   FLOAT_BLEND_OPTIMIZATION_ENABLE      REG_BIT(4)
 
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 756807c4b405..73b59ea6fd3b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2178,6 +2178,16 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
                wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
        }
 
+       if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
+           IS_DG2_G10(i915)) {
+               /* Wa_22014600077:dg2 */
+               wa_add(wal, GEN10_CACHE_MODE_SS, 0,
+                      _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
+                      0 /* Wa_14012342262 :write-only reg, so skip
+                           verification */,
+                      true);
+       }
+
        if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
            IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0)) {
                /*
-- 
2.20.1