From: Badal Nilawar <badal.nila...@intel.com>

Even though PVC doesn't have an RCS engine, this workaround updates a
register in the 0x2xxx range that traditionally belongs to the RCS.  We
need to set a special flag to tell the GuC that the presence of an "RCS"
register on a CCS save/restore list is okay/expected.

Cc: Stuart Summers <stuart.summ...@intel.com>
Cc: Lucas De Marchi <lucas.demar...@intel.com>
Signed-off-by: Badal Nilawar <badal.nila...@intel.com>
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
 drivers/gpu/drm/i915/gt/uc/intel_guc.c      | 4 ++++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
 4 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 6aa1ceaa8d27..1986579b18ba 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -140,6 +140,7 @@
 #define FF_SLICE_CS_CHICKEN2                   _MMIO(0x20e4)
 #define   GEN9_TSG_BARRIER_ACK_DISABLE         (1 << 8)
 #define   GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE    (1 << 10)
+#define   GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15)
 
 #define GEN9_CS_DEBUG_MODE1                    _MMIO(0x20ec)
 #define   FF_DOP_CLOCK_GATE_DISABLE            REG_BIT(1)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6e875d4f5f65..eb0598593724 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2698,6 +2698,11 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
                /* Wa_22014226127:dg2,pvc */
                wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
        }
+
+       /* Wa_16015675438:pvc */
+       if (IS_PVC_BD_STEP(i915, STEP_B0, STEP_FOREVER))
+               wa_masked_en(wal, FF_SLICE_CS_CHICKEN2,
+                            GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 2c4ad4a65089..7043cf5a666a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -327,6 +327,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
            IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
                flags |= GUC_WA_CONTEXT_ISOLATION;
 
+       /* Wa_16015675438:pvc */
+       if (IS_PVC_BD_STEP(gt->i915, STEP_B0, STEP_FOREVER))
+               flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
+
        return flags;
 }
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
index 42cb7a9a6199..b3c9a9327f76 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
@@ -105,6 +105,7 @@
 #define   GUC_WA_PRE_PARSER            BIT(14)
 #define   GUC_WA_HOLD_CCS_SWITCHOUT    BIT(17)
 #define   GUC_WA_POLLCS                        BIT(18)
+#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST     BIT(21)
 
 #define GUC_CTL_FEATURE                        2
 #define   GUC_CTL_ENABLE_SLPC          BIT(2)
-- 
2.35.3

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