On Mon, Jun 06, 2022 at 11:33:24AM +0530, Anshuman Gupta wrote: > i915 must disable Render DOP clock gating globally. > > B.Spec: 52621 > Cc: Matt Roper <matthew.d.ro...@intel.com> > Cc: Badal Nilawar <badal.nila...@intel.com> > Signed-off-by: Anshuman Gupta <anshuman.gu...@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++ > 2 files changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 58e9b464d564..55a291ab5536 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -630,6 +630,7 @@ > > #define GEN7_MISCCPCTL _MMIO(0x9424) > #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0) > +#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE (1 << 1)
We should use a tab (instead of spaces) between the register name and the bit definition. We should probably switch to 'REG_BIT' notation for new bits being added too. > #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) > #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) > #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index a604bc7c0701..b957dec64eee 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -1489,6 +1489,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct > i915_wa_list *wal) > * performance guide section. > */ > wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS); > + > + /* > + * Wa_14015795083 > + */ We can just use a single-line comment here. Aside from these cosmetic issues (and the formatting of 'Bspec' that Jani noted), Reviewed-by: Matt Roper <matthew.d.ro...@intel.com> > + wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); > } > > static void > -- > 2.26.2 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation
