Hi, On Tue, Jul 05, 2022 at 12:57:18PM +0200, Karolina Drobnik wrote: > From: Chris Wilson <ch...@chris-wilson.co.uk> > > In monitoring a transcode pipeline that is latency sensitive (it waits > between submitting frames, and each frame requires work on rcs/vcs/vecs > engines), it is found that it took longer than a single jiffy for it to > sustain its workload. Allowing an extra jiffy headroom for the userspace > prevents us from prematurely parking and having to exit powersaving > immediately. > > Link: https://gitlab.freedesktop.org/drm/intel/-/issues/6284 > Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk> > Signed-off-by: Karolina Drobnik <karolina.drob...@intel.com>
Reviewed-by: Andi Shyti <andi.sh...@linux.intel.com> Andi > --- > drivers/gpu/drm/i915/i915_active.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_active.c > b/drivers/gpu/drm/i915/i915_active.c > index ee2b3a375362..7412abf166a8 100644 > --- a/drivers/gpu/drm/i915/i915_active.c > +++ b/drivers/gpu/drm/i915/i915_active.c > @@ -974,7 +974,7 @@ void i915_active_acquire_barrier(struct i915_active *ref) > > GEM_BUG_ON(!intel_engine_pm_is_awake(engine)); > llist_add(barrier_to_ll(node), &engine->barrier_tasks); > - intel_engine_pm_put_delay(engine, 1); > + intel_engine_pm_put_delay(engine, 2); > } > } > > -- > 2.25.1
