Move display hdport related members under drm_i915_private display
sub-struct.

Prefer adding anonymous sub-structs even for single members that aren't
our own structs.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c          |  4 ++--
 drivers/gpu/drm/i915/display/intel_display.c      |  2 +-
 drivers/gpu/drm/i915/display/intel_display_core.h | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c     |  4 ++--
 drivers/gpu/drm/i915/i915_drv.h                   |  8 --------
 5 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index f5416433826d..266c379c1d98 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4130,8 +4130,8 @@ intel_ddi_max_lanes(struct intel_digital_port *dig_port)
 
 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
 {
-       return i915->hti_state & HDPORT_ENABLED &&
-              i915->hti_state & HDPORT_DDI_USED(phy);
+       return i915->display.hdport.hti_state & HDPORT_ENABLED &&
+              i915->display.hdport.hti_state & HDPORT_DDI_USED(phy);
 }
 
 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 7834a47e0b4b..2160537fee73 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8774,7 +8774,7 @@ int intel_modeset_init_nogem(struct drm_i915_private 
*i915)
         * any display resources before we create our display outputs.
         */
        if (INTEL_INFO(i915)->display.has_hti)
-               i915->hti_state = intel_de_read(i915, HDPORT_STATE);
+               i915->display.hdport.hti_state = intel_de_read(i915, 
HDPORT_STATE);
 
        /* Just disable it once at startup */
        intel_vga_disable(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 4c9a6b9c5512..eb013c153c48 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -355,6 +355,16 @@ struct intel_display {
                struct mutex comp_mutex;
        } hdcp;
 
+       struct {
+               /*
+                * HTI (aka HDPORT) state read during initial hw readout.  Most
+                * platforms don't have HTI, so this will just stay 0.  Those
+                * that do will use this later to figure out which PLLs and PHYs
+                * are unavailable for driver usage.
+                */
+               u32 hti_state;
+       } hdport;
+
        struct {
                bool enabled;
        } ipc;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d437fcf04bdd..8260f1168e8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -3169,10 +3169,10 @@ static void icl_update_active_dpll(struct 
intel_atomic_state *state,
 
 static u32 intel_get_hti_plls(struct drm_i915_private *i915)
 {
-       if (!(i915->hti_state & HDPORT_ENABLED))
+       if (!(i915->display.hdport.hti_state & HDPORT_ENABLED))
                return 0;
 
-       return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->hti_state);
+       return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, 
i915->display.hdport.hti_state);
 }
 
 static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c95c75714da..ae63a8d71392 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -305,14 +305,6 @@ struct drm_i915_private {
 
        struct intel_l3_parity l3_parity;
 
-       /*
-        * HTI (aka HDPORT) state read during initial hw readout.  Most
-        * platforms don't have HTI, so this will just stay 0.  Those that do
-        * will use this later to figure out which PLLs and PHYs are unavailable
-        * for driver usage.
-        */
-       u32 hti_state;
-
        /*
         * edram size in MB.
         * Cannot be determined by PCIID. You must always read a register.
-- 
2.34.1

Reply via email to