[Intel-gfx] [PATCH 12/12] drm/i915/mtl: Add multicast steering for media GT

[Matt Roper]

MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1.  We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).

Bspec: 67789
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_mcr.c      | 19 +++++++++++++++++--
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++++++++++-
 3 files changed, 35 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c 
b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 05f41f1cc88d..04f75c1e0f4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -41,6 +41,7 @@ static const char * const intel_steering_types[] = {
        "MSLICE",
        "LNCF",
        "DSS",
+       "OADDRM",
        "INSTANCE 0",
 };
 
@@ -119,6 +120,12 @@ static const struct intel_mmio_range 
mtl3d_dss_steering_table[] = {
        { 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
 };
 
+static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
+       { 0x393200, 0x39323F },
+       { 0x393400, 0x3934FF },
+};
+
+
 void intel_gt_mcr_init(struct intel_gt *gt)
 {
        struct drm_i915_private *i915 = gt->i915;
@@ -141,8 +148,9 @@ void intel_gt_mcr_init(struct intel_gt *gt)
                        drm_warn(&i915->drm, "mslice mask all zero!\n");
        }
 
-       if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
-           gt->type == GT_PRIMARY) {
+       if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
+               gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
+       } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
                fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
                                     intel_uncore_read(gt->uncore, XEHP_FUSE4));
 
@@ -435,6 +443,13 @@ static void get_nonterminated_steering(struct intel_gt *gt,
                *group = 0;
                *instance = 0;
                break;
+       case OADDRM:
+               if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & 
BIT(0))
+                       *group = 0;
+               else
+                       *group = 1;
+               *instance = 0;
+               break;
        default:
                MISSING_CASE(type);
                *group = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 2a0441410ec7..5fa59a66dba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -60,6 +60,7 @@ enum intel_steering_type {
        MSLICE,
        LNCF,
        DSS,
+       OADDRM,
 
        /*
         * On some platforms there are multiple types of MCR registers that
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2562ad83966b..9227391fc144 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1585,12 +1585,28 @@ mtl_3d_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
        }
 }
 
+static void
+mtl_media_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+       /*
+        * Unlike older platforms, we no longer setup implicit steering here;
+        * all MCR accesses are explicitly steered.
+        */
+       if (drm_debug_enabled(DRM_UT_DRIVER)) {
+               struct drm_printer p = drm_debug_printer("MCR Steering:");
+
+               intel_gt_mcr_report_steering(&p, gt, false);
+       }
+}
+
 static void
 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
 {
        struct drm_i915_private *i915 = gt->i915;
 
-       if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
+       if (IS_METEORLAKE(i915) && gt->type == GT_MEDIA)
+               mtl_media_gt_workarounds_init(gt, wal);
+       else if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
                mtl_3d_gt_workarounds_init(gt, wal);
        else if (IS_PONTEVECCHIO(i915))
                pvc_gt_workarounds_init(gt, wal);
-- 
2.37.3