On Wed, Nov 27, 2013 at 09:16:42PM +0530, deepa...@intel.com wrote:
> From: Deepak S <deepa...@intel.com>
>
> On VLV, FIFO will be shared by both SW and HW.
SW I take it means MMIO access coming from the CPU, and HW means eg.
LRI from some CS?
Are there any docs clearly stating this? The Gunit HAS is next to
useless trying to figure out how the internal register accesses
get routed.
> So, we read the
> free entries through register and update dev_priv variable
> and wait for only 20 entries to be free
>
> Signed-off-by: Deepak S <deepa...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_uncore.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
> b/drivers/gpu/drm/i915/intel_uncore.c
> index eac5661..3e7848a 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -147,6 +147,12 @@ static int __gen6_gt_wait_for_fifo(struct
> drm_i915_private *dev_priv)
> {
> int ret = 0;
>
> + /* On VLV, FIFO will be shared by both SW and HW.
> + * So, we need to read the FREE_ENTRIES everytime */
> + if (IS_VALLEYVIEW(dev_priv->dev))
> + dev_priv->uncore.fifo_count =
> + __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
This would need to mask the free entries. I sent out a patch to fix the
already existing cases, but you'd need to do it here too.
> +
> if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
> int loop = 500;
> u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
> --
> 1.8.4.2
>
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--
Ville Syrjälä
Intel OTC
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