Hi Chris, In VLV, both hardware and software can use the write fifo in parallel, we are adding this change as a water mark to make sure we atleast have 20 free entries .This will help us to avoid software mmio write being dropped.
Thanks Deepak -----Original Message----- From: Chris Wilson [mailto:ch...@chris-wilson.co.uk] Sent: Friday, November 29, 2013 4:09 PM To: S, Deepak Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH v2] drm/i915/vlv: Update Wait for FIFO and wait for 20 free entries. v2 On Fri, Nov 29, 2013 at 03:44:31PM +0530, deepa...@intel.com wrote: > From: Deepak S <deepa...@intel.com> > > On VLV, FIFO will be shared by both SW and HW. So, we read the free > entries through register and update dev_priv variable and wait for > only 20 entries to be free But the whole point of leaving 20 entries is for hardware has a portion of the fifo it can use for its own nefarious deeds. The hw has been emitting mmio through the write fifo since its inception on gen6, so what is so different for vlv? -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
