DDI_CLK_SEL is an another macro which returns the register offset based
on DDI port enum. So DDI_CLK_SEL has to be prepared for the new method
being developed for calculating the register offsets of DDI ports.
Macro receives i915 private structure as new parameter for the upcoming
changes.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanan...@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 17 +++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 5 ++++-
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 77a986696c76..e7beafafb857 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -305,7 +305,8 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder
*encoder,
static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
enum port port)
{
- u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
+ u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(dev_priv, port)) &
+ DDI_CLK_SEL_MASK;
switch (val) {
case DDI_CLK_SEL_NONE:
@@ -1656,7 +1657,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder
*encoder,
* "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the
port.
* MG does not exist, but the programming is required to ungate DDIC
and DDID."
*/
- intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
+ intel_de_write(i915, DDI_CLK_SEL(i915, port), DDI_CLK_SEL_MG);
icl_ddi_combo_enable_clock(encoder, crtc_state);
}
@@ -1668,7 +1669,7 @@ static void jsl_ddi_tc_disable_clock(struct intel_encoder
*encoder)
icl_ddi_combo_disable_clock(encoder);
- intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+ intel_de_write(i915, DDI_CLK_SEL(i915, port), DDI_CLK_SEL_NONE);
}
static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
@@ -1677,7 +1678,7 @@ static bool jsl_ddi_tc_is_clock_enabled(struct
intel_encoder *encoder)
enum port port = encoder->port;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(i915, DDI_CLK_SEL(i915, port));
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
return false;
@@ -1696,7 +1697,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder
*encoder,
if (drm_WARN_ON(&i915->drm, !pll))
return;
- intel_de_write(i915, DDI_CLK_SEL(port),
+ intel_de_write(i915, DDI_CLK_SEL(i915, port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
mutex_lock(&i915->display.dpll.lock);
@@ -1720,7 +1721,7 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder
*encoder)
mutex_unlock(&i915->display.dpll.lock);
- intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
+ intel_de_write(i915, DDI_CLK_SEL(i915, port), DDI_CLK_SEL_NONE);
}
static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
@@ -1730,7 +1731,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct
intel_encoder *encoder)
enum port port = encoder->port;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(i915, DDI_CLK_SEL(i915, port));
if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
return false;
@@ -1748,7 +1749,7 @@ static struct intel_shared_dpll
*icl_ddi_tc_get_pll(struct intel_encoder *encode
enum intel_dpll_id id;
u32 tmp;
- tmp = intel_de_read(i915, DDI_CLK_SEL(port));
+ tmp = intel_de_read(i915, DDI_CLK_SEL(i915, port));
switch (tmp & DDI_CLK_SEL_MASK) {
case DDI_CLK_SEL_TBT_162:
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a91bbc6e1255..acb764755338 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7075,7 +7075,10 @@ enum skl_power_gate {
#define PORT_CLK_SEL_NONE REG_FIELD_PREP(PORT_CLK_SEL_MASK, 7)
/* On ICL+ this is the same as PORT_CLK_SEL, but all bits change. */
-#define DDI_CLK_SEL(port) PORT_CLK_SEL(port)
+#define DDI_CLK_SEL(i915, port) ({ \
+ (void)i915; /* Suppress unused
variable warning */ \
+ PORT_CLK_SEL(port); \
+ })
#define DDI_CLK_SEL_MASK REG_GENMASK(31, 28)
#define DDI_CLK_SEL_NONE REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
#define DDI_CLK_SEL_MG
REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
--
2.34.1
