On Fri, 21 Oct 2022, Balasubramani Vivekanandan
<balasubramani.vivekanan...@intel.com> wrote:
> On 20.10.2022 17:20, Anusha Srivatsa wrote:
>> Driver had discrepancy in how cdclk squash and crawl support
>> were checked. Like crawl, add squash as a 1 bit feature flag
>> to the display section of DG2.
>>
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanan...@intel.com>
>> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 15 +++++----------
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/i915_pci.c | 1 +
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> 4 files changed, 8 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 0f5add2fc51b..45babbc6290f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -1220,11 +1220,6 @@ static void skl_cdclk_uninit_hw(struct
>> drm_i915_private *dev_priv)
>> skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
>> }
>>
>> -static bool has_cdclk_squash(struct drm_i915_private *i915)
>> -{
>> - return IS_DG2(i915);
>> -}
>> -
>> struct intel_cdclk_vals {
>> u32 cdclk;
>> u16 refclk;
>> @@ -1520,7 +1515,7 @@ static void bxt_get_cdclk(struct drm_i915_private
>> *dev_priv,
>> return;
>> }
>>
>> - if (has_cdclk_squash(dev_priv))
>> + if (HAS_CDCLK_SQUASH(dev_priv))
>> squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
>>
>> if (squash_ctl & CDCLK_SQUASH_ENABLE) {
>> @@ -1747,7 +1742,7 @@ static void bxt_set_cdclk(struct drm_i915_private
>> *dev_priv,
>> else
>> clock = cdclk;
>>
>> - if (has_cdclk_squash(dev_priv)) {
>> + if (HAS_CDCLK_SQUASH(dev_priv)) {
>> u32 squash_ctl = 0;
>>
>> if (waveform)
>> @@ -1845,7 +1840,7 @@ static void bxt_sanitize_cdclk(struct drm_i915_private
>> *dev_priv)
>> expected = skl_cdclk_decimal(cdclk);
>>
>> /* Figure out what CD2X divider we should be using for this cdclk */
>> - if (has_cdclk_squash(dev_priv))
>> + if (HAS_CDCLK_SQUASH(dev_priv))
>> clock = dev_priv->display.cdclk.hw.vco / 2;
>> else
>> clock = dev_priv->display.cdclk.hw.cdclk;
>> @@ -1976,7 +1971,7 @@ static bool intel_cdclk_can_squash(struct
>> drm_i915_private *dev_priv,
>> * the moment all platforms with squasher use a fixed cd2x
>> * divider.
>> */
>> - if (!has_cdclk_squash(dev_priv))
>> + if (!HAS_CDCLK_SQUASH(dev_priv))
>> return false;
>>
>> return a->cdclk != b->cdclk &&
>> @@ -2028,7 +2023,7 @@ static bool intel_cdclk_can_cd2x_update(struct
>> drm_i915_private *dev_priv,
>> * the moment all platforms with squasher use a fixed cd2x
>> * divider.
>> */
>> - if (has_cdclk_squash(dev_priv))
>> + if (HAS_CDCLK_SQUASH(dev_priv))
>> return false;
>>
>> return a->cdclk != b->cdclk &&
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index d7b8eb9d4117..db51050e3ba2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -869,6 +869,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define HAS_DOUBLE_BUFFERED_M_N(dev_priv) (DISPLAY_VER(dev_priv) >= 9 ||
>> IS_BROADWELL(dev_priv))
>>
>> #define HAS_CDCLK_CRAWL(dev_priv)
>> (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
>> +#define HAS_CDCLK_SQUASH(dev_priv)
>> (INTEL_INFO(dev_priv)->display.has_cdclk_squash)
>> #define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
>> #define HAS_FPGA_DBG_UNCLAIMED(dev_priv)
>> (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index 19bf5ef6a20d..a88e1439a426 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -1064,6 +1064,7 @@ static const struct intel_device_info xehpsdv_info = {
>> .has_guc_deprivilege = 1, \
>> .has_heci_pxp = 1, \
>> .has_media_ratio_mode = 1, \
>> + .display.has_cdclk_squash = 1, \
>
> Shouldn't this line be under dg2_info definition and not here?
It's in DG2_FEATURES macro, which is where it should be. You're probably
thrown off by the diff context symbol xehpsdv_info.
BR,
Jani.
>
> Regards,
> Bala
>
>> .__runtime.platform_engine_mask = \
>> BIT(RCS0) | BIT(BCS0) | \
>> BIT(VECS0) | BIT(VECS1) | \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index cdf78728dcad..67d8759c802c 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -180,6 +180,7 @@ enum intel_ppgtt_type {
>> /* Keep in alphabetical order */ \
>> func(cursor_needs_physical); \
>> func(has_cdclk_crawl); \
>> + func(has_cdclk_squash); \
>> func(has_ddi); \
>> func(has_dp_mst); \
>> func(has_dsb); \
>> --
>> 2.25.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
