From: Deepak S <deepa...@intel.com> On VLV the PCBR register has other bits besides the pcbr address field. Verify only address field setup by BIOS to make sure we don't misinterpret the PCBR setup.
Signed-off-by: Deepak S <deepa...@intel.com> --- drivers/gpu/drm/i915/intel_pm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e6d98fe..2e1340f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4036,7 +4036,12 @@ static void valleyview_setup_pctx(struct drm_device *dev) int pctx_size = 24*1024; pcbr = I915_READ(VLV_PCBR); - if (pcbr) { + + /* PCBR Format: Bits 31:12 - Base address of Process Context + * Bits 11:1 - Reserved + * Bit 0 - PCBR Lock + * Check only address field if already setup by BIOS */ + if (pcbr >> 12) { /* BIOS set it up already, grab the pre-alloc'd space */ int pcbr_offset; -- 1.8.4.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx