> -----Original Message-----
> From: Intel-gfx <intel-gfx-boun...@lists.freedesktop.org> On Behalf Of
> Stanislav Lisovskiy
> Sent: Thursday, November 24, 2022 2:36 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nik...@intel.com>
> Subject: [Intel-gfx] [PATCH 1/1] drm/i915: Implement workaround for CDCLK
> PLL disable/enable
> 
> It was reported that we might get a hung and loss of register access in some
> cases when CDCLK PLL is disabled and then enabled, while squashing is
> enabled.
> As a workaround it was proposed by HW team that SW should disable
> squashing when CDCLK PLL is being reenabled.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 0c107a38f9d0..e338f288c9ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1801,6 +1801,13 @@ static bool
> cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
>       return true;
>  }
> 
> +static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) {
> +     return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv))
> +             && dev_priv->display.cdclk.hw.vco > 0
> +             && HAS_CDCLK_SQUASH(dev_priv));
Redundant check. If it is MTL or DG2, then it will have HAS_CDCLK_SQUASH set to 
true always. Shouldn't vco be 0 instead of > 0. The commit message says the 
hang can be observed when moving from 0 to > 0 vco. 

Anusha
> +}
> +
>  static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
>                          const struct intel_cdclk_config *cdclk_config,
>                          enum pipe pipe)
> @@ -1815,9 +1822,12 @@ static void _bxt_set_cdclk(struct
> drm_i915_private *dev_priv,
>           !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
>               if (dev_priv->display.cdclk.hw.vco != vco)
>                       adlp_cdclk_pll_crawl(dev_priv, vco);
> -     } else if (DISPLAY_VER(dev_priv) >= 11)
> +     } else if (DISPLAY_VER(dev_priv) >= 11) {
> +             if (pll_enable_wa_needed(dev_priv))
> +                     dg2_cdclk_squash_program(dev_priv, 0);
> +
>               icl_cdclk_pll_update(dev_priv, vco);
> -     else
> +     } else
>               bxt_cdclk_pll_update(dev_priv, vco);
> 
>       waveform = cdclk_squash_waveform(dev_priv, cdclk);
> --
> 2.37.3

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