Pass the i915 pointer to the macros where needed.
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
.../gpu/drm/i915/display/intel_backlight.c | 38 +++++++++----------
.../drm/i915/display/intel_backlight_regs.h | 6 +--
2 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 71af88a70461..b3c44b054d08 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -159,7 +159,7 @@ static u32 i9xx_get_backlight(struct intel_connector
*connector, enum pipe unuse
struct intel_panel *panel = &connector->panel;
u32 val;
- val = intel_de_read(dev_priv, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
+ val = intel_de_read(dev_priv, BLC_PWM_CTL(dev_priv)) &
BACKLIGHT_DUTY_CYCLE_MASK;
if (DISPLAY_VER(dev_priv) < 4)
val >>= 1;
@@ -244,8 +244,8 @@ static void i9xx_set_backlight(const struct
drm_connector_state *conn_state, u32
mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;
}
- tmp = intel_de_read(dev_priv, BLC_PWM_CTL) & ~mask;
- intel_de_write(dev_priv, BLC_PWM_CTL, tmp | level);
+ tmp = intel_de_read(dev_priv, BLC_PWM_CTL(dev_priv)) & ~mask;
+ intel_de_write(dev_priv, BLC_PWM_CTL(dev_priv), tmp | level);
}
static void vlv_set_backlight(const struct drm_connector_state *conn_state,
u32 level)
@@ -383,8 +383,8 @@ static void i965_disable_backlight(const struct
drm_connector_state *old_conn_st
intel_backlight_set_pwm_level(old_conn_state, val);
- tmp = intel_de_read(dev_priv, BLC_PWM_CTL2);
- intel_de_write(dev_priv, BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
+ tmp = intel_de_read(dev_priv, BLC_PWM_CTL2(dev_priv));
+ intel_de_write(dev_priv, BLC_PWM_CTL2(dev_priv), tmp & ~BLM_PWM_ENABLE);
}
static void vlv_disable_backlight(const struct drm_connector_state
*old_conn_state, u32 val)
@@ -585,10 +585,10 @@ static void i9xx_enable_backlight(const struct
intel_crtc_state *crtc_state,
struct intel_panel *panel = &connector->panel;
u32 ctl, freq;
- ctl = intel_de_read(dev_priv, BLC_PWM_CTL);
+ ctl = intel_de_read(dev_priv, BLC_PWM_CTL(dev_priv));
if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) {
drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n");
- intel_de_write(dev_priv, BLC_PWM_CTL, 0);
+ intel_de_write(dev_priv, BLC_PWM_CTL(dev_priv), 0);
}
freq = panel->backlight.pwm_level_max;
@@ -601,8 +601,8 @@ static void i9xx_enable_backlight(const struct
intel_crtc_state *crtc_state,
if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm)
ctl |= BLM_POLARITY_PNV;
- intel_de_write(dev_priv, BLC_PWM_CTL, ctl);
- intel_de_posting_read(dev_priv, BLC_PWM_CTL);
+ intel_de_write(dev_priv, BLC_PWM_CTL(dev_priv), ctl);
+ intel_de_posting_read(dev_priv, BLC_PWM_CTL(dev_priv));
/* XXX: combine this into above write? */
intel_backlight_set_pwm_level(conn_state, level);
@@ -613,7 +613,7 @@ static void i9xx_enable_backlight(const struct
intel_crtc_state *crtc_state,
* that has backlight.
*/
if (DISPLAY_VER(dev_priv) == 2)
- intel_de_write(dev_priv, BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
+ intel_de_write(dev_priv, BLC_HIST_CTL(dev_priv),
BLM_HISTOGRAM_ENABLE);
}
static void i965_enable_backlight(const struct intel_crtc_state *crtc_state,
@@ -625,11 +625,11 @@ static void i965_enable_backlight(const struct
intel_crtc_state *crtc_state,
enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;
u32 ctl, ctl2, freq;
- ctl2 = intel_de_read(dev_priv, BLC_PWM_CTL2);
+ ctl2 = intel_de_read(dev_priv, BLC_PWM_CTL2(dev_priv));
if (ctl2 & BLM_PWM_ENABLE) {
drm_dbg_kms(&dev_priv->drm, "backlight already enabled\n");
ctl2 &= ~BLM_PWM_ENABLE;
- intel_de_write(dev_priv, BLC_PWM_CTL2, ctl2);
+ intel_de_write(dev_priv, BLC_PWM_CTL2(dev_priv), ctl2);
}
freq = panel->backlight.pwm_level_max;
@@ -637,16 +637,16 @@ static void i965_enable_backlight(const struct
intel_crtc_state *crtc_state,
freq /= 0xff;
ctl = freq << 16;
- intel_de_write(dev_priv, BLC_PWM_CTL, ctl);
+ intel_de_write(dev_priv, BLC_PWM_CTL(dev_priv), ctl);
ctl2 = BLM_PIPE(pipe);
if (panel->backlight.combination_mode)
ctl2 |= BLM_COMBINATION_MODE;
if (panel->backlight.active_low_pwm)
ctl2 |= BLM_POLARITY_I965;
- intel_de_write(dev_priv, BLC_PWM_CTL2, ctl2);
- intel_de_posting_read(dev_priv, BLC_PWM_CTL2);
- intel_de_write(dev_priv, BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
+ intel_de_write(dev_priv, BLC_PWM_CTL2(dev_priv), ctl2);
+ intel_de_posting_read(dev_priv, BLC_PWM_CTL2(dev_priv));
+ intel_de_write(dev_priv, BLC_PWM_CTL2(dev_priv), ctl2 | BLM_PWM_ENABLE);
intel_backlight_set_pwm_level(conn_state, level);
}
@@ -1326,7 +1326,7 @@ static int i9xx_setup_backlight(struct intel_connector
*connector, enum pipe unu
struct intel_panel *panel = &connector->panel;
u32 ctl, val;
- ctl = intel_de_read(dev_priv, BLC_PWM_CTL);
+ ctl = intel_de_read(dev_priv, BLC_PWM_CTL(dev_priv));
if (DISPLAY_VER(dev_priv) == 2 || IS_I915GM(dev_priv) ||
IS_I945GM(dev_priv))
panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
@@ -1364,11 +1364,11 @@ static int i965_setup_backlight(struct intel_connector
*connector, enum pipe unu
struct intel_panel *panel = &connector->panel;
u32 ctl, ctl2;
- ctl2 = intel_de_read(dev_priv, BLC_PWM_CTL2);
+ ctl2 = intel_de_read(dev_priv, BLC_PWM_CTL2(dev_priv));
panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE;
panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
- ctl = intel_de_read(dev_priv, BLC_PWM_CTL);
+ ctl = intel_de_read(dev_priv, BLC_PWM_CTL(dev_priv));
panel->backlight.pwm_level_max = ctl >> 16;
if (!panel->backlight.pwm_level_max)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight_regs.h
b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
index 02bd1f8201bf..385faafcfcf5 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_backlight_regs.h
@@ -21,7 +21,7 @@
#define VLV_BLC_HIST_CTL(pipe) _MMIO_PIPE(pipe, _VLV_BLC_HIST_CTL_A,
_VLV_BLC_HIST_CTL_B)
/* Backlight control */
-#define BLC_PWM_CTL2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61250) /* 965+
only */
+#define BLC_PWM_CTL2(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x61250) /*
965+ only */
#define BLM_PWM_ENABLE (1 << 31)
#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
#define BLM_PIPE_SELECT (1 << 29)
@@ -44,7 +44,7 @@
#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
#define BLM_PHASE_IN_INCR_SHIFT (0)
#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
-#define BLC_PWM_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61254)
+#define BLC_PWM_CTL(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x61254)
/*
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
@@ -66,7 +66,7 @@
#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
-#define BLC_HIST_CTL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61260)
+#define BLC_HIST_CTL(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x61260)
#define BLM_HISTOGRAM_ENABLE (1 << 31)
/* New registers for PCH-split platforms. Safe where new bits show up, the
--
2.34.1
