On Fri, Dec 02, 2022 at 03:44:09PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> 
> Account for the framestart delay when calculating the "pipeline full"
> value for icl/tgl vrr. This puts the start of vblank (ie. where the
> double bufferd registers get latched) to a consistent place regardless
> of what framestart delay value is used. framestart delay does not
> change where start of vblank occurs in non-vrr mode and I can't see
> any reason why we'd want different behaviour in vrr mode.
> 
> Currently framestart delay is always set to 1, and the hardcoded 4
> scanlines in the code means we're currently delaying the start of
> vblank by three extra lines. And with framestart delay set to 4 we'd
> have no extra delay.
> 
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>

So now basically if we want to delay the vblank, then we will need to
update framestart_delay to somethin other than 1.
Currently with framestart_delay = 1, there is no vblank delay, its just
vrr.vmin - vdisplay so the vblank start right after?

Is this the correct understanding?

Anyway, if this logic is validated to work then should be fine.
Basically this will only impact display <13, so as long as we dont
regress anything on TGL then we should be good.

Reviewed-by: Manasi Navare <manasi.d.nav...@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 13 ++-----------
>  1 file changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 7b1357e82b69..6655dd2c1684 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -153,18 +153,9 @@ intel_vrr_compute_config(struct intel_crtc_state 
> *crtc_state,
>               crtc_state->vrr.guardband =
>                       crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
>       } else {
> -             /*
> -              * FIXME: s/4/framestart_delay/ to get consistent
> -              * earliest/latest points for register latching regardless
> -              * of the framestart_delay used?
> -              *
> -              * FIXME: this really needs the extra scanline to provide 
> consistent
> -              * behaviour for all framestart_delay values. Otherwise with
> -              * framestart_delay==4 we will end up extending the min vblank 
> by
> -              * one extra line.
> -              */
>               crtc_state->vrr.pipeline_full =
> -                     min(255, crtc_state->vrr.vmin - 
> adjusted_mode->crtc_vdisplay - 4 - 1);
> +                     min(255, crtc_state->vrr.vmin - 
> adjusted_mode->crtc_vdisplay -
> +                         crtc_state->framestart_delay - 1);
>       }
>  
>       crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> -- 
> 2.37.4
> 

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