On Wed, Jan 11, 2023 at 03:55:23PM -0800, Radhakrishna Sripada wrote:
> From: Lucas De Marchi <lucas.demar...@intel.com>
>
> Commit 0d0e7d1eea9e ("drm/i915/mtl: Define engine context layouts")
> added the engine context for Meteor Lake. In a second revision of the
> patch it was believed the xcs offsets were wrong due to a tagging
> issue in the spec. The first version was actually correct, as shown
> by the intel_lrc_live_selftests/live_lrc_layout test:
>
> i915: Running gt_lrc
> i915: Running intel_lrc_live_selftests/live_lrc_layout
> bcs0: LRI command mismatch at dword 1, expected 1108101d found 11081019
> [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]]
> [CONNECTOR:236:DP-1] disconnected
> bcs0: HW register image:
> [0000] 00000000 1108101d 00022244 ffff0008 00022034 00000088 00022030
> 00000088
> ...
> bcs0: SW register image:
> [0000] 00000000 11081019 00022244 00090009 00022034 00000000 00022030
> 00000000
>
> The difference in the 2 additional dwords (0x1d vs 0x19) are the offsets
> 0x120 / 0x124 that are indeed part of the context image.
>
> Bspec: 45585
>
> Fixes: 0d0e7d1eea9e ("drm/i915/mtl: Define engine context layouts")
> Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
> Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
I'll poke the bspec people about getting the platform information fixed
for this so that we don't run into confusion here again.
Matt
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 37 +----------------------------
> 1 file changed, 1 insertion(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
> b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 7771a19008c6..bbeeb6dde7ae 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -288,39 +288,6 @@ static const u8 dg2_xcs_offsets[] = {
> END
> };
>
> -static const u8 mtl_xcs_offsets[] = {
> - NOP(1),
> - LRI(13, POSTED),
> - REG16(0x244),
> - REG(0x034),
> - REG(0x030),
> - REG(0x038),
> - REG(0x03c),
> - REG(0x168),
> - REG(0x140),
> - REG(0x110),
> - REG(0x1c0),
> - REG(0x1c4),
> - REG(0x1c8),
> - REG(0x180),
> - REG16(0x2b4),
> - NOP(4),
> -
> - NOP(1),
> - LRI(9, POSTED),
> - REG16(0x3a8),
> - REG16(0x28c),
> - REG16(0x288),
> - REG16(0x284),
> - REG16(0x280),
> - REG16(0x27c),
> - REG16(0x278),
> - REG16(0x274),
> - REG16(0x270),
> -
> - END
> -};
> -
> static const u8 gen8_rcs_offsets[] = {
> NOP(1),
> LRI(14, POSTED),
> @@ -739,9 +706,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs
> *engine)
> else
> return gen8_rcs_offsets;
> } else {
> - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70))
> - return mtl_xcs_offsets;
> - else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
> return dg2_xcs_offsets;
> else if (GRAPHICS_VER(engine->i915) >= 12)
> return gen12_xcs_offsets;
> --
> 2.34.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
