> -----Original Message-----
> From: Kandpal, Suraj <suraj.kand...@intel.com>
> Sent: Wednesday, January 11, 2023 11:09 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nautiyal, Ankit K <ankit.k.nauti...@intel.com>; Kulkarni, Vandita
> <vandita.kulka...@intel.com>; Navare, Manasi D
> <manasi.d.nav...@intel.com>; Kandpal, Suraj <suraj.kand...@intel.com>
> Subject: [PATCH v6 3/9] drm/i915: Adding the new registers for DSC
>
> Adding new DSC register which are introducted MTL onwards
>
> Signed-off-by: Suraj Kandpal <suraj.kand...@intel.com>
Reviewed-by: Vandita Kulkarni <vandita.kulka...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 8b2cf980f323..69a645ce0fe8
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7766,6 +7766,8 @@ enum skl_power_gate {
> #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)
> _MMIO_PIPE((pipe) - PIPE_B, \
>
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
>
> _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define DSC_NATIVE_422_ENABLE BIT(23)
> +#define DSC_NATIVE_420_ENABLE BIT(22)
> #define DSC_ALT_ICH_SEL (1 << 20)
> #define DSC_VBR_ENABLE (1 << 19)
> #define DSC_422_ENABLE (1 << 18)
> @@ -8010,6 +8012,32 @@ enum skl_power_gate {
> #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) <<
> 16)
> #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size)
> ((slice_chunk_size) << 0)
>
> +/* MTL Display Stream Compression registers */
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4
> +#define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe)
> _MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC)
> +#define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)
> _MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
> +#define DSC_SL_BPG_OFFSET(offset) ((offset) << 27)
> +
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8
> +#define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8
> +#define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8
> +#define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe)
> _MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \
> +
> _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC)
> +#define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)
> _MMIO_PIPE((pipe) - PIPE_B, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
> +
> _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
> +#define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16)
> +#define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0)
> +
> /* Icelake Rate Control Buffer Threshold Registers */
> #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230)
> #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4)
> --
> 2.25.1
