Re: [Intel-gfx] [PATCH v4 1/2] drm/i915/dg2: Introduce Wa_18018764978

[Tvrtko Ursulin]

On 28/11/2022 18:26, Matt Roper wrote:
On Wed, Nov 23, 2022 at 04:45:25PM -0300, Gustavo Sousa wrote:
On Wed, Nov 23, 2022 at 10:36:47AM -0800, Matt Atwood wrote:
Wa_18018764978 applies to specific steppings of DG2 (G10 C0+,
G11 and G12 A0+). Clean up style in function at the same time.

Bspec: 66622

Signed-off-by: Matt Atwood <matthew.s.atw...@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.so...@intel.com>

Both patches applied to drm-intel-gt-next.  Thanks for the patches and
review.

Do these need to be sent to 6.2 fixes, given DG2 is out of force probe 
there?

Regards,

Tvrtko

---
  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 3 +++
  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 ++++++-
  2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 80a979e6f6be..74379d3c5a4d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -457,6 +457,9 @@
  #define GEN8_L3CNTLREG                                _MMIO(0x7034)
  #define   GEN8_ERRDETBCTRL                    (1 << 9)
  
+#define PSS_MODE2				_MMIO(0x703c)
+#define   SCOREBOARD_STALL_FLUSH_CONTROL       REG_BIT(5)
+
  #define GEN7_SC_INSTDONE                      _MMIO(0x7100)
  #define GEN12_SC_INSTDONE_EXTRA                       _MMIO(0x7104)
  #define GEN12_SC_INSTDONE_EXTRA2              _MMIO(0x7108)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2afb4f80a954..870db5a202dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -771,9 +771,14 @@ static void dg2_ctx_workarounds_init(struct 
intel_engine_cs *engine,
  
  	/* Wa_14014947963:dg2 */
        if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
-               IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+           IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
                wa_masked_field_set(wal, VF_PREEMPTION, 
PREEMPTION_VERTEX_COUNT, 0x4000);
  
+	/* Wa_18018764978:dg2 */
+       if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_C0, STEP_FOREVER) ||
+           IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+               wa_masked_en(wal, PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL);
+
        /* Wa_15010599737:dg2 */
        wa_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN);
  }
--
2.38.1