On Wed, Feb 01, 2023 at 02:28:28PM -0800, Matt Roper wrote:
> XEHPC_LNCFMISCCFGREG0 and XEHPC_L3SCRUB are both in MCR register ranges
> on PVC (with HALFBSLICE and L3BANK replication respectively), so they
> should be explicitly declared as MCR registers and use MCR-aware
> workaround handlers.
>
> The workarounds/tuning settings should still be applied properly on PVC
> even without the MCR annotation, but readback verification on
> CONFIG_DRM_I915_DEBUG_GEM builds could potentitally give false positive
> "workaround lost on load" warnings on parts fused such that a unicast
> read targets a terminated register instance.
>
> Fixes: a9e69428b1b4 ("drm/i915: Define MCR registers explicitly")
> Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.so...@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 4 ++--
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 +++++++++---
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 7fa18a3b3957..928698c621e5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -979,7 +979,7 @@
> #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
> #define GEN7_L3AGDIS (1 << 19)
>
> -#define XEHPC_LNCFMISCCFGREG0 _MMIO(0xb01c)
> +#define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c)
> #define XEHPC_HOSTCACHEEN REG_BIT(1)
> #define XEHPC_OVRLSCCC REG_BIT(0)
>
> @@ -1042,7 +1042,7 @@
> #define XEHP_L3SCQREG7 MCR_REG(0xb188)
> #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
>
> -#define XEHPC_L3SCRUB _MMIO(0xb18c)
> +#define XEHPC_L3SCRUB MCR_REG(0xb18c)
> #define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12)
> #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
> #define SCRUB_RATE_4B_PER_CLK
> REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 29718d0595f4..f45ca3d4a07c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -240,6 +240,12 @@ wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32
> set)
> wa_write_clr_set(wal, reg, ~0, set);
> }
>
> +static void
> +wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
> +{
> + wa_mcr_write_clr_set(wal, reg, ~0, set);
> +}
> +
> static void
> wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
> {
> @@ -2892,9 +2898,9 @@ add_render_compute_tuning_settings(struct
> drm_i915_private *i915,
> struct i915_wa_list *wal)
> {
> if (IS_PONTEVECCHIO(i915)) {
> - wa_write(wal, XEHPC_L3SCRUB,
> + wa_mcr_write(wal, XEHPC_L3SCRUB,
> SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
> - wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
> + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN);
> }
>
> if (IS_DG2(i915)) {
> @@ -2984,7 +2990,7 @@ general_render_compute_wa_init(struct intel_engine_cs
> *engine, struct i915_wa_li
>
> if (IS_PONTEVECCHIO(i915)) {
> /* Wa_16016694945 */
> - wa_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> + wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC);
> }
>
> if (IS_XEHPSDV(i915)) {
> --
> 2.39.1
>
