[Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess

[Ville Syrjala]

From: Ville Syrjälä <ville.syrj...@linux.intel.com>

The DSI code has some local hacks to program TRANS_H/VBLANK on
TGL+ (ICL DSI transcoders didn't have these registers). That
will not work when we need to start using the delayed vblank
(for DSB purposes). Too lazy to figure out what the is going
on there, so just sprinkle FIXMEs in the hopes someone else
will spot them eventually.

Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c       | 7 ++++++-
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c 
b/drivers/gpu/drm/i915/display/icl_dsi.c
index def3aff4d717..b5316715bb3b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -957,7 +957,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder 
*encoder,
                }
        }
 
-       /* program TRANS_VBLANK register, should be same as vtotal programmed */
+       /*
+        * program TRANS_VBLANK register, should be same as vtotal programmed
+        *
+        * FIXME get rid of these local hacks and do it right,
+        * this will not handle eg. delayed vblank correctly.
+        */
        if (DISPLAY_VER(dev_priv) >= 12) {
                for_each_dsi_port(port, intel_dsi->ports) {
                        dsi_trans = dsi_port_to_transcoder(port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index 92306246e907..4210ede5e52e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2938,6 +2938,7 @@ static void intel_get_transcoder_timings(struct 
intel_crtc *crtc,
        adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
        adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
 
+       /* FIXME TGL+ DSI transcoders have this! */
        if (!transcoder_is_dsi(cpu_transcoder)) {
                tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
                adjusted_mode->crtc_hblank_start = 
REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
@@ -2952,6 +2953,7 @@ static void intel_get_transcoder_timings(struct 
intel_crtc *crtc,
        adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
        adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
 
+       /* FIXME TGL+ DSI transcoders have this! */
        if (!transcoder_is_dsi(cpu_transcoder)) {
                tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
                adjusted_mode->crtc_vblank_start = 
REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
@@ -2967,6 +2969,7 @@ static void intel_get_transcoder_timings(struct 
intel_crtc *crtc,
                adjusted_mode->crtc_vblank_end += 1;
        }
 
+       /* FIXME ADL+ DSI transcoders have this! */
        if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
                adjusted_mode->crtc_vblank_start =
                        adjusted_mode->crtc_vdisplay +
-- 
2.39.1