[Intel-gfx] [PATCH 1/2] drm/i915/mtl: Add workarounds Wa_14017066071 and Wa_14017654203

[Gustavo Sousa]

From: Radhakrishna Sripada <radhakrishna.srip...@intel.com>

Both workarounds require the same implementation and apply to MTL P and
M from stepping A0 to B0 (exclusive).

Signed-off-by: Radhakrishna Sripada <radhakrishna.srip...@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.so...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     |  1 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 12 ++++++++++--
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h 
b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4aecb5a7b631..1ec855813632 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1144,6 +1144,7 @@
 #define   ENABLE_SMALLPL                       REG_BIT(15)
 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB    REG_BIT(9)
 #define   GEN11_SAMPLER_ENABLE_HEADLESS_MSG    REG_BIT(5)
+#define   MTL_DISABLE_SAMPLER_SC_OOO           REG_BIT(3)
 
 #define GEN9_HALF_SLICE_CHICKEN7               MCR_REG(0xe194)
 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA      REG_BIT(15)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e7ee24bcad89..cafdf66d9562 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2388,11 +2388,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
        struct drm_i915_private *i915 = engine->i915;
 
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
-           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
+           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
                /* Wa_22014600077 */
                wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS,
                                 ENABLE_EU_COUNT_FOR_TDL_FLUSH);
-       }
 
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
@@ -2971,6 +2970,15 @@ general_render_compute_wa_init(struct intel_engine_cs 
*engine, struct i915_wa_li
 
        add_render_compute_tuning_settings(i915, wal);
 
+       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
+           IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0))
+               /*
+                * Wa_14017066071
+                * Wa_14017654203
+                */
+               wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+                                MTL_DISABLE_SAMPLER_SC_OOO);
+
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0) ||
            IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
-- 
2.40.0