On Tue, 09 May 2023 10:25:16 -0700, Dixit, Ashutosh wrote: > > On Fri, 05 May 2023 17:58:14 -0700, Umesh Nerlige Ramappa wrote: > > > > From: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > > > > We do not want to have timers per tile and waste CPU cycles and energy via > > multiple wake-up sources, for a relatively un-important task of PMU > > sampling, so keeping a single timer works well. But we also do not want > > the first GT which goes idle to turn off the timer. > > Apart from this efficiency, what is the reason for having a device level > PMU (which monitors gt level events), rather than independent gt level > PMU's (each of which monitor events from that gt)? > > Wouldn't independent gt level PMU's be simpler? And user space tools (say > intel-gpu-top) would hook into events from a gt and treat each gt > independently? > > So my question really is what is the reason for keeping the PMU device > level rather than per gt?
Maybe ignore this for now, the way it is expressed it is too open ended. Let me get a better handle on the code and the patches and I'll see if I have anything to say. Thanks. -- Ashutosh
