[Intel-gfx] [PATCH v2 1/5] drm/i915/dg2: Recognize pre-production hardware

[Matt Roper]

The first production SoC steppings for DG2 were C0 (for G10), B1 (for
G11), and A1 (for G12).  This corresponds to PCI revision IDs 0x8, 0x5,
and 0x1 respectively.  Add this information to the driver's
pre-production detection.

Bspec: 44477
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Acked-by: Jani Nikula <jani.nik...@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atw...@intel.com>
---
 drivers/gpu/drm/i915/i915_driver.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_driver.c 
b/drivers/gpu/drm/i915/i915_driver.c
index b870c0df081a..0201115746a7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -183,6 +183,9 @@ static void intel_detect_preproduction_hw(struct 
drm_i915_private *dev_priv)
        pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
        pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
        pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
+       pre |= IS_DG2_G10(dev_priv) && INTEL_REVID(dev_priv) < 0x8;
+       pre |= IS_DG2_G11(dev_priv) && INTEL_REVID(dev_priv) < 0x5;
+       pre |= IS_DG2_G12(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 
        if (pre) {
                drm_err(&dev_priv->drm, "This is a pre-production stepping. "
-- 
2.41.0