Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
for Xe2_LPD and will allow to see the delta more easily.
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
.../drm/i915/display/intel_display_device.c | 60 ++++++++++++++++---
1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index c39f8a15d8aa..089674e2f1d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -710,18 +710,62 @@ static const struct intel_display_device_info
xe_hpd_display = {
BIT(PORT_TC1),
};
+#define XE_LPDP_FEATURES
\
+ .abox_mask = GENMASK(1, 0),
\
+ .color = {
\
+ .degamma_lut_size = 129, .gamma_lut_size = 1024,
\
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |
\
+ DRM_COLOR_LUT_EQUAL_CHANNELS,
\
+ },
\
+ .dbuf.size = 4096,
\
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |
\
+ BIT(DBUF_S4),
\
+ .has_cdclk_crawl = 1,
\
+ .has_cdclk_squash = 1,
\
+ .has_ddi = 1,
\
+ .has_dp_mst = 1,
\
+ .has_dsb = 1,
\
+ .has_fpga_dbg = 1,
\
+ .has_hotplug = 1,
\
+ .has_ipc = 1,
\
+ .has_psr = 1,
\
+ .pipe_offsets = {
\
+ [TRANSCODER_A] = PIPE_A_OFFSET,
\
+ [TRANSCODER_B] = PIPE_B_OFFSET,
\
+ [TRANSCODER_C] = PIPE_C_OFFSET,
\
+ [TRANSCODER_D] = PIPE_D_OFFSET,
\
+ [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,
\
+ [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,
\
+ },
\
+ .trans_offsets = {
\
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET,
\
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET,
\
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET,
\
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET,
\
+ [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,
\
+ [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,
\
+ },
\
+ TGL_CURSOR_OFFSETS,
\
+
\
+ .__runtime_defaults.cpu_transcoder_mask =
\
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
\
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
\
+ .__runtime_defaults.ip.ver = 13,
\
+ .__runtime_defaults.has_dmc = 1,
\
+ .__runtime_defaults.has_dsc = 1,
\
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
\
+ .__runtime_defaults.has_hdcp = 1,
\
+ .__runtime_defaults.pipe_mask =
\
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
\
+ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
\
+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
+
+
static const struct intel_display_device_info xe_lpdp_display = {
- XE_LPD_FEATURES,
- .has_cdclk_crawl = 1,
- .has_cdclk_squash = 1,
+ XE_LPDP_FEATURES,
.__runtime_defaults.ip.ver = 14,
.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
- .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
- BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
};
/*
--
2.40.1
