[Intel-gfx] [PATCH v2 23/27] drm/i915/lnl: Start using CDCLK through PLL

[Lucas De Marchi]

From: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>

Introduce correspondent definitions and for choosing between CD2X CDCLK
and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are
defined with PLL CDCLK as source, so simply set it.

v2:
  - Remove unneeded comment and use REG_BIT() (Matt Roper)
  - Rename CDCLK_SOURCE_SEL_CDCLK_PLL() to MDCLK_SOURCE_SEL_CDCLK_PLL
    to match spec (Lucas)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovs...@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 9 +++++++--
 drivers/gpu/drm/i915/i915_reg.h            | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 7307af2a4af5..abe845906c7c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1906,8 +1906,7 @@ static void _bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
                dg2_cdclk_squash_program(dev_priv, waveform);
 
        val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
-               bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-               skl_cdclk_decimal(cdclk);
+               bxt_cdclk_cd2x_pipe(dev_priv, pipe);
 
        /*
         * Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1916,6 +1915,12 @@ static void _bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
        if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
            cdclk >= 500000)
                val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+       if (DISPLAY_VER(dev_priv) >= 20)
+               val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
+       else
+               val |= skl_cdclk_decimal(cdclk);
+
        intel_de_write(dev_priv, CDCLK_CTL, val);
 
        if (pipe != INVALID_PIPE)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efcf1461988f..c59eb411cf06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5884,6 +5884,7 @@ enum skl_power_gate {
 #define  CDCLK_FREQ_540                REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
 #define  CDCLK_FREQ_337_308            REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
 #define  CDCLK_FREQ_675_617            REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define  MDCLK_SOURCE_SEL_CDCLK_PLL    REG_BIT(25)
 #define  BXT_CDCLK_CD2X_DIV_SEL_MASK   REG_GENMASK(23, 22)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1      
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
 #define  BXT_CDCLK_CD2X_DIV_SEL_1_5    
REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
-- 
2.40.1