Apply Wa_16018031267 / Wa_16018063123. This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.
v2:
- Rename old platform check in second patch to match
declaration in first patch.
- Refactor second patch name to match first patch.
v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.
v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
check_ring_start during lrc live selftest.
v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
command streams.
- No longer skip on empty, as command stream will never
be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
fragment from INDIRECT_CTX setup).
v7:
- Use 0x6b instead of 0 for color to maintain functionality.
Signed-off-by: Nirmoy Das <nirmoy....@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cav...@intel.com>
CC: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.v...@intel.com>
CC: Tomasz Mistat <tomasz.mis...@intel.com>
CC: Gregory F Germano <gregory.f.germ...@intel.com>
CC: Matt Roper <matthew.d.ro...@intel.com>
CC: James Ausmus <james.aus...@intel.com>
Jonathan Cavitt (2):
drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
drm/i915: Set copy engine arbitration for Wa_16018031267 /
Wa_16018063123
drivers/gpu/drm/i915/gt/intel_engine_regs.h | 6 ++
drivers/gpu/drm/i915/gt/intel_gt.h | 4 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 102 +++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
drivers/gpu/drm/i915/gt/selftest_lrc.c | 65 +++++++++----
6 files changed, 163 insertions(+), 21 deletions(-)
--
2.25.1
