Re: [Intel-gfx] [PATCH] drm/i915/gt: skip WA verfication for GEN7_MISCCPCTL on DG2

[Andrzej Hajda]

On 12.09.2023 09:35, Andrzej Hajda wrote:

Some DG2 firmware locks this register for modification. Using wa_add
with read_mask 0 allows to skip checks of such registers.

Signed-off-by: Andrzej Hajda <andrzej.ha...@intel.com>

Forgot to add tag:
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8945

Regards
Andrzej

---
  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 70071ead0659cc..1d1474ad945e0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1597,8 +1597,11 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct 
i915_wa_list *wal)
        /* Wa_14014830051:dg2 */
        wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);

- /* Wa_14015795083 */

-       wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
+       /* Wa_14015795083
+        * Skip verification for possibly locked register.
+        */
+       wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE,
+              0, 0, false);

/* Wa_18018781329 */

        wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);