On Mon, Sep 11, 2023 at 09:48:32PM -0700, Lucas De Marchi wrote: > From: Stanislav Lisovskiy <[email protected]> > > Add a new CDCLK table for Lunar Lake. > > v2: > - Remove mdclk from the table as it's not needed (Matt Roper) > - Update waveform values to the latest from spec (Matt Roper) > - Rename functions and calculation to match by pixel rate (Lucas) > v3: Keep only the table: as far as intel_pixel_rate_to_cdclk() > is concerned, the minimum cdclk should still be half the pixel > rate on Xe2 (bspec 68858: > "Pipe maximum pixel rate = 2 * CDCLK frequency * Pipe Ratio") > (Matt Roper) > > Bspec: 68861, 68858 > Signed-off-by: Stanislav Lisovskiy <[email protected]> > Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 656ff50def39..4cde78db83a1 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1382,6 +1382,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] > = { > {} > }; > > +static const struct intel_cdclk_vals lnl_cdclk_table[] = { > + { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, > .waveform = 0xaaaa }, > + { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, > .waveform = 0xad5a }, > + { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, > .waveform = 0xb6b6 }, > + { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, > .waveform = 0xdbb6 }, > + { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, > .waveform = 0xeeee }, > + { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, > .waveform = 0xf7de }, > + { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, > .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, > .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, > .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, > .waveform = 0xdbb6 }, > + { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, > .waveform = 0xeeee }, > + { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, > .waveform = 0xf7de }, > + { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, > .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, > .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, > .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, > .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, > .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, > .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, > .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, > .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, > .waveform = 0xffff }, > + {} > +}; > + > static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) > { > const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; > @@ -3591,7 +3616,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs > = { > */ > void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > { > - if (DISPLAY_VER(dev_priv) >= 14) { > + if (DISPLAY_VER(dev_priv) >= 20) { > + dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; > + dev_priv->display.cdclk.table = lnl_cdclk_table; > + } else if (DISPLAY_VER(dev_priv) >= 14) { > dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; > dev_priv->display.cdclk.table = mtl_cdclk_table; > } else if (IS_DG2(dev_priv)) { > -- > 2.40.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
