Set copy engine arbitration into round robin mode
for part of Wa_16018031267 / Wa_16018063123 mitigation.

Signed-off-by: Nirmoy Das <nirmoy....@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cav...@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_regs.h | 3 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_regs.h 
b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
index b8618ee3e3041..c0c8c12edea10 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_regs.h
@@ -124,6 +124,9 @@
 #define RING_INDIRECT_CTX(base)                        _MMIO((base) + 0x1c4) 
/* gen8+ */
 #define RING_INDIRECT_CTX_OFFSET(base)         _MMIO((base) + 0x1c8) /* gen8+ 
*/
 #define ECOSKPD(base)                          _MMIO((base) + 0x1d0)
+#define   XEHP_BLITTER_SCHEDULING_MODE_MASK    REG_GENMASK(12, 11)
+#define   XEHP_BLITTER_ROUND_ROBIN_MODE                \
+               REG_FIELD_PREP(XEHP_BLITTER_SCHEDULING_MODE_MASK, 1)
 #define   ECO_CONSTANT_BUFFER_SR_DISABLE       REG_BIT(4)
 #define   ECO_GATING_CX_ONLY                   REG_BIT(3)
 #define   GEN6_BLITTER_FBC_NOTIFY              REG_BIT(3)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 660d4f358eab7..b8f3b991e4202 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2781,6 +2781,11 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, 
struct i915_wa_list *wal)
                         RING_SEMA_WAIT_POLL(engine->mmio_base),
                         1);
        }
+       /* Wa_16018031267, Wa_16018063123 */
+       if (NEEDS_FASTCOLOR_BLT_WABB(engine))
+               wa_masked_field_set(wal, ECOSKPD(engine->mmio_base),
+                                   XEHP_BLITTER_SCHEDULING_MODE_MASK,
+                                   XEHP_BLITTER_ROUND_ROBIN_MODE);
 }
 
 static void
-- 
2.25.1

Reply via email to