Quoting Lucas De Marchi (2023-10-18 19:24:41-03:00)
>With MTL adding PICA between the port and the real phy, the path
>add for DG2 stopped being followed and newer platforms are simply using
>the older path for TC phys. LNL is no different than MTL in this aspect,
>so just add it to the mess. In future the phy and port designation and
>deciding if it's TC should better be cleaned up.
>
>To make it just a bit better, also change intel_phy_is_snps() to show
>this is DG2-only.
>
>Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 29 ++++++++++----------
> 1 file changed, 15 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>b/drivers/gpu/drm/i915/display/intel_display.c
>index 28d85e1e858e..0797ace31417 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -1784,31 +1784,32 @@ bool intel_phy_is_combo(struct drm_i915_private
>*dev_priv, enum phy phy)
>
> bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
> {
>+ /* DG2's "TC1" output uses a SNPS PHY and is handled separately */
> if (IS_DG2(dev_priv))
>- /* DG2's "TC1" output uses a SNPS PHY */
> return false;
>- else if (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER_FULL(dev_priv) ==
>IP_VER(14, 0))
>+
>+ /*
>+ * TODO: This should mostly match intel_port_to_phy(), considering the
>+ * ports already encode if they are connected to a TC phy in their
>name.
>+ */
>+ if (IS_LUNARLAKE(dev_priv) || IS_METEORLAKE(dev_priv) ||
>+ IS_ALDERLAKE_P(dev_priv))
Just like already done with the previous patch, I think we should have a
paragraph in the commit message justifying s/DISPLAY_VER_FULL(dev_priv) ==
IP_VER(14, 0)/IS_METEORLAKE(dev_priv)/.
With that in place,
Reviewed-by: Gustavo Sousa <gustavo.so...@intel.com>
> return phy >= PHY_F && phy <= PHY_I;
> else if (IS_TIGERLAKE(dev_priv))
> return phy >= PHY_D && phy <= PHY_I;
> else if (IS_ICELAKE(dev_priv))
> return phy >= PHY_C && phy <= PHY_F;
>- else
>- return false;
>+
>+ return false;
> }
>
> bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
> {
>- if (phy == PHY_NONE)
>- return false;
>- else if (IS_DG2(dev_priv))
>- /*
>- * All four "combo" ports and the TC1 port (PHY E) use
>- * Synopsis PHYs.
>- */
>- return phy <= PHY_E;
>-
>- return false;
>+ /*
>+ * For DG2, and for DG2 only, all four "combo" ports and the TC1 port
>+ * (PHY E) use Synopsis PHYs.
>+ */
>+ return IS_DG2(dev_priv) && phy > PHY_NONE && phy <= PHY_E;
> }
>
> enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
>--
>2.40.1
>
