On Wed, 18 Oct 2023, Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com> wrote: > eDP specification supports HBR3 link rate since v1.4a. Moreover, > C10 phy can support HBR3 link rate for both DP and eDP. Therefore, > do not clamp the supported rates for eDP at 6.75Gbps. > > Cc: <sta...@vger.kernel.org> > > BSpec: 70073 74224 > > Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.bo...@intel.com>
For future reference, the trailers (Cc, Bspec, Signed-off-by, etc.) all go together with no blank lines in between. BR, Jani. > --- > drivers/gpu/drm/i915/display/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 1891c0cc187d..2c1034578984 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -430,7 +430,7 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) > enum phy phy = intel_port_to_phy(i915, dig_port->base.port); > > if (intel_is_c10phy(i915, phy)) > - return intel_dp_is_edp(intel_dp) ? 675000 : 810000; > + return 810000; > > return 2000000; > } -- Jani Nikula, Intel
