[Intel-gfx] [PATCH] drm/i915: Fix fractional bpp handling in intel_link_bw_reduce_bpp()

[Imre Deak]

Convert crtc_state->pipe_bpp to U6.4 format as expected by the rest of
the function.

Fixes: 59a266f068b4 ("drm/i915/display: Store compressed bpp in U6.4 format")
Cc: Ankit Nautiyal <ankit.k.nauti...@intel.com>
Cc: Suraj Kandpal <suraj.kand...@intel.com>
Cc: Sui Jingfeng <suijingf...@loongson.cn>
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_link_bw.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c 
b/drivers/gpu/drm/i915/display/intel_link_bw.c
index 02a0af2aa5bae..9c6d35a405a18 100644
--- a/drivers/gpu/drm/i915/display/intel_link_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_link_bw.c
@@ -55,11 +55,11 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state 
*state,
        struct drm_i915_private *i915 = to_i915(state->base.dev);
        enum pipe max_bpp_pipe = INVALID_PIPE;
        struct intel_crtc *crtc;
-       int max_bpp = 0;
+       int max_bpp_x16 = 0;
 
        for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
                struct intel_crtc_state *crtc_state;
-               int link_bpp;
+               int link_bpp_x16;
 
                if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe))
                        continue;
@@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
                        return PTR_ERR(crtc_state);
 
                if (crtc_state->dsc.compression_enable)
-                       link_bpp = crtc_state->dsc.compressed_bpp_x16;
+                       link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
                else
                        /*
                         * TODO: for YUV420 the actual link bpp is only half
@@ -78,10 +78,10 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state 
*state,
                         * is based on the pipe bpp value, set the actual link 
bpp
                         * limit here once the MST BW allocation is fixed.
                         */
-                       link_bpp = crtc_state->pipe_bpp;
+                       link_bpp_x16 = to_bpp_x16(crtc_state->pipe_bpp);
 
-               if (link_bpp > max_bpp) {
-                       max_bpp = link_bpp;
+               if (link_bpp_x16 > max_bpp_x16) {
+                       max_bpp_x16 = link_bpp_x16;
                        max_bpp_pipe = crtc->pipe;
                }
        }
@@ -89,7 +89,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state,
        if (max_bpp_pipe == INVALID_PIPE)
                return -ENOSPC;
 
-       limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1;
+       limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1;
 
        return intel_modeset_pipes_in_mask_early(state, reason,
                                                 BIT(max_bpp_pipe));
-- 
2.39.2