On Wed, 03 Jan 2024, Arun R Murthy <arun.r.mur...@intel.com> wrote: > With a value of '0' read from MSTM_CAP register MST to be enabled. > DP2.1 SCR updates the spec for 128/132b DP capable supporting only one > stream and not supporting single stream sideband MSG. > The underlying protocol will be MST to enable use of MTP. > > Signed-off-by: Arun R Murthy <arun.r.mur...@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 9ff0cbd9c0df..40d3280f8d98 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -4038,8 +4038,13 @@ intel_dp_configure_mst(struct intel_dp *intel_dp) > if (!intel_dp_mst_source_support(intel_dp)) > return; > > - intel_dp->is_mst = sink_can_mst && > - i915->display.params.enable_dp_mst; > + /* > + * Even if dpcd reg MSTM_CAP is 0, if the sink supports UHBR rates then > + * DP2.1 can be enabled with underlying protocol using MST for MTP > + */ > + intel_dp->is_mst = (sink_can_mst || > + > drm_dp_is_uhbr_rate(intel_dp_max_common_rate(intel_dp))) > + && i915->display.params.enable_dp_mst;
We use drm_dp_is_uhbr_rate() in intel_dp_is_uhbr() to determine whether the link rate in the *crtc state* is uhbr, and by proxy whether the link in the *crtc state* is 128b/132b. There, we've already decided to use uhbr and 128b/132b. This one here is different, and I think it's taking us to the wrong direction. For example, it should be possible to downgrade the link from uhbr to non-uhbr on link failures. We don't have that yet. But this makes untangling that even harder. BR, Jani. > > drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, > intel_dp->is_mst); -- Jani Nikula, Intel
