This patch is first extension to color manager framework. It adds implementataion of color manager property CSC correction (wide gamute) in intel color manager framework.
Signed-off-by: Shashank Sharma <shashank.sha...@intel.com> --- drivers/gpu/drm/i915/intel_clrmgr.c | 117 +++++++++++++++++++++++++++++++++-- 1 file changed, 112 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_clrmgr.c b/drivers/gpu/drm/i915/intel_clrmgr.c index 2c826f3..363e3e6 100644 --- a/drivers/gpu/drm/i915/intel_clrmgr.c +++ b/drivers/gpu/drm/i915/intel_clrmgr.c @@ -146,11 +146,6 @@ static bool intel_clrmgr_disable_gamma(struct drm_device *dev, int identifier) { return true; } - -static void intel_clrmgr_disable_csc(struct drm_device *dev, int identifier) -{ -} - static bool intel_clrmgr_enable_hs(struct drm_device *dev, int identifier) { return true; @@ -165,8 +160,120 @@ static bool intel_clrmgr_enable_gamma(struct drm_device *dev, int identifier) return true; } +/* +* intel_disable_csc +* Disable color space conversion on PIPE +* idenifier is pipe identifier +*/ +void +intel_disable_csc(struct drm_device *dev, int identifier) +{ + u32 pipeconf = 0; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (_validate_pipe(identifier)) + return; + + /* Disable CSC on PIPE */ + pipeconf = I915_READ(PIPECONF(identifier)); + pipeconf &= ~(PIPECONF_CSC_ENABLE); + I915_WRITE(PIPECONF(identifier), pipeconf); + POSTING_READ(PIPECONF(identifier)); + + DRM_DEBUG_DRIVER("CSC disabled on PIPE %c\n", + identifier == pipe_a ? 'A' : 'B'); + + return; +} + +/* +* intel_clrmgr_disable_csc +* Disable property CSC +* identifier = pipe identifier +*/ +static void intel_clrmgr_disable_csc(struct drm_device *dev, int identifier) +{ + drm_i915_private_t *dev_priv = dev->dev_private; + struct clrmgr_pipe_status *pstatus = dev_priv->clrmgr_status.pstatus; + + if (!pstatus) { + DRM_ERROR("Clrmgr: color manager not initialized"); + return; + } + + intel_disable_csc(dev, identifier); + pstatus->csc_enabled = false; + DRM_DEBUG_DRIVER("Clrmgr: CSC disabled\n"); +} + +/* +* intel_enable_csc +* Enable color space conversion on PIPE +* data is correction values to be written +* identifier is pipe identifier +*/ +int +intel_enable_csc(struct drm_device *dev, u32 *data, int identifier) +{ + int count = 0; + int pipe = 0; + u32 csc_reg = 0; + u32 pipeconf = 0; + struct drm_i915_private *dev_priv = dev->dev_private; + + if (!data) { + DRM_ERROR("NULL input to enable CSC"); + return -EINVAL; + } + + if (identifier != pipe_a) { + DRM_ERROR("CSC is supported on PIPEA only for now"); + return -EINVAL; + } + + pipeconf = I915_READ(PIPECONF(identifier)); + pipeconf |= PIPECONF_CSC_ENABLE; + csc_reg = PIPECSC(identifier); + + /* Enable csc correction */ + I915_WRITE(PIPECONF(identifier), pipeconf); + POSTING_READ(PIPECONF(identifier)); + + /* Write csc coeff to csc regs */ + while (count < CSC_MAX_COEFF_COUNT) { + I915_WRITE(csc_reg + (4 * count), ((u32 *)data)[count]); + count++; + } + + DRM_DEBUG_DRIVER("CSC enabled on PIPE %c\n", + pipe == pipe_a ? 'A' : 'B'); + + return 0; +} + +/* +* intel_clrmgr_enable_csc +* Enable property CSC +* identifier = pipe identifier +*/ static bool intel_clrmgr_enable_csc(struct drm_device *dev, int identifier) { + drm_i915_private_t *dev_priv = dev->dev_private; + struct clrmgr_pipe_status *pstatus = dev_priv->clrmgr_status.pstatus; + + if (!pstatus) { + DRM_ERROR("Clrmgr: color manager not initialized"); + return false; + } + + if (intel_enable_csc(dev, clrmgr_luts[clrmgr_csc], + identifier)) { + DRM_ERROR("Clrmgr: Enable CSC failed"); + return false; + } + + pstatus->csc_enabled = true; + DRM_DEBUG_DRIVER("Clrmgr: CSC Enabled"); return true; } -- 1.7.10.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx