On Wed, 03 Apr 2024, Balasubramani Vivekanandan
<balasubramani.vivekanan...@intel.com> wrote:
> From: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
>
> Enable RM timeout interrupt to detect any hang during display engine
> register access. This interrupt is supported only on Display version 14.
> Current default timeout is 2ms.
>
> WA: 14012195489
Please don't invent new trailers. Add proper wa descriptions in
comments.
> Bspec: 50110
>
There should be no blank line here.
> CC: Suraj Kandpal <suraj.kand...@intel.com>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
> Signed-off-by: Balasubramani Vivekanandan
> <balasubramani.vivekanan...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_irq.c | 10 ++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index f846c5b108b5..3035b50fcad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -851,6 +851,13 @@ gen8_de_misc_irq_handler(struct drm_i915_private
> *dev_priv, u32 iir)
> {
> bool found = false;
>
> + if (iir & GEN8_DE_RM_TIMEOUT) {
> + u32 val = intel_uncore_read(&dev_priv->uncore,
> + RMTIMEOUTREG_CAPTURE);
> + drm_warn(&dev_priv->drm, "Register Access Timeout = 0x%x\n",
> val);
What good does this do with no information on the register?
> + found = true;
> + }
> +
> if (DISPLAY_VER(dev_priv) >= 14) {
> if (iir & (XELPDP_PMDEMAND_RSP |
> XELPDP_PMDEMAND_RSPTOUT_ERR)) {
> @@ -1666,6 +1673,9 @@ void gen8_de_irq_postinstall(struct drm_i915_private
> *dev_priv)
> de_port_masked |= DSI0_TE | DSI1_TE;
> }
>
> + if (DISPLAY_VER(dev_priv) == 14)
> + de_misc_masked |= GEN8_DE_RM_TIMEOUT;
> +
> de_pipe_enables = de_pipe_masked |
> GEN8_PIPE_VBLANK |
> gen8_de_pipe_underrun_mask(dev_priv) |
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 875d76fb8cd0..d1692b32bb8a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4212,6 +4212,8 @@
> #define RM_TIMEOUT _MMIO(0x42060)
> #define MMIO_TIMEOUT_US(us) ((us) << 0)
>
> +#define RMTIMEOUTREG_CAPTURE _MMIO(0x420e0)
> +
> /* interrupts */
> #define DE_MASTER_IRQ_CONTROL (1 << 31)
> #define DE_SPRITEB_FLIP_DONE (1 << 29)
> @@ -4398,6 +4400,7 @@
> #define GEN8_DE_MISC_IMR _MMIO(0x44464)
> #define GEN8_DE_MISC_IIR _MMIO(0x44468)
> #define GEN8_DE_MISC_IER _MMIO(0x4446c)
> +#define GEN8_DE_RM_TIMEOUT REG_BIT(29)
> #define XELPDP_PMDEMAND_RSPTOUT_ERR REG_BIT(27)
> #define GEN8_DE_MISC_GSE REG_BIT(27)
> #define GEN8_DE_EDP_PSR REG_BIT(19)
--
Jani Nikula, Intel
