On Wed, Apr 03, 2024 at 04:52:40PM +0530, Balasubramani Vivekanandan wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapa...@intel.com>
>
> DP/eDP and HDMI pll values are updated for Xe2_HPD platform
>
> Bspec: 74165
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapa...@intel.com>
> Signed-off-by: Balasubramani Vivekanandan
> <balasubramani.vivekanan...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 47 +++++++++++++++++++-
> 1 file changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index d948035f07ad..20035be015c3 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -1109,6 +1109,42 @@ static const struct intel_c20pll_state * const
> xe2hpd_c20_edp_tables[] = {
> NULL,
> };
>
> +static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = {
> + .clock = 1350000, /* 13.5 Gbps */
> + .tx = { 0xbea0, /* tx cfg0 */
> + 0x4800, /* tx cfg1 */
> + 0x0000, /* tx cfg2 */
> + },
> + .cmn = {0x0500, /* cmn cfg0*/
> + 0x0005, /* cmn cfg1 */
> + 0x0000, /* cmn cfg2 */
> + 0x0000, /* cmn cfg3 */
> + },
> + .mpllb = { 0x015f, /* mpllb cfg0 */
> + 0x2205, /* mpllb cfg1 */
> + 0x1b17, /* mpllb cfg2 */
> + 0xffc1, /* mpllb cfg3 */
> + 0xbd00, /* mpllb cfg4 */
> + 0x9ec3, /* mpllb cfg5 */
> + 0x2000, /* mpllb cfg6 */
> + 0x0001, /* mpllb cfg7 */
> + 0x4800, /* mpllb cfg8 */
> + 0x0000, /* mpllb cfg9 */
> + 0x0000, /* mpllb cfg10 */
> + },
> +};
> +
> +static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = {
> + &mtl_c20_dp_rbr,
> + &mtl_c20_dp_hbr1,
> + &mtl_c20_dp_hbr2,
> + &mtl_c20_dp_hbr3,
> + &mtl_c20_dp_uhbr10,
> + &xe2hpd_c20_dp_uhbr13_5,
> + &mtl_c20_dp_uhbr20,
According to bspec 67066, I don't think we need the UHBR20 table for
Xe2_HPD (even though there are data values given on page 74165).
Otherwise,
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
Matt
> + NULL,
> +};
> +
> /*
> * HDMI link rates with 38.4 MHz reference clock.
> */
> @@ -2225,13 +2261,20 @@ static const struct intel_c20pll_state * const *
> intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> - if (intel_crtc_has_dp_encoder(crtc_state))
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> + if (intel_crtc_has_dp_encoder(crtc_state)) {
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> return xe2hpd_c20_edp_tables;
> +
> + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> + return xe2hpd_c20_dp_tables;
> else
> return mtl_c20_dp_tables;
> - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +
> + } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> return mtl_c20_hdmi_tables;
> + }
>
> MISSING_CASE(encoder->type);
> return NULL;
> --
> 2.25.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
