On Thu, Apr 25, 2024 at 11:22:30AM GMT, Matt Roper wrote:
On Thu, Apr 25, 2024 at 11:16:09AM -0700, Lucas De Marchi wrote:
Contrary to i915, in xe ADL-N is kept as a different platform, not a
subplatform of ADL-P. Since the display side doesn't need to
differentiate between P and N, i.e. IS_ALDERLAKE_P_N() is never called,
just fixup the compat header to check for both P and N.
Moving ADL-N to be a subplatform would be more complex as the firmware
loading in xe only handles platforms, not subplatforms, as going forward
the direction is to check on IP version rather than
platforms/subplatforms.
Fix warning when initializing display:
xe 0000:00:02.0: [drm:intel_pch_type [xe]] Found Alder Lake PCH
------------[ cut here ]------------
xe 0000:00:02.0: drm_WARN_ON(!((dev_priv)->info.platform == XE_ALDERLAKE_S)
&& !((dev_priv)->info.platform == XE_ALDERLAKE_P))
And wrong paths being taken on the display side.
Signed-off-by: Lucas De Marchi <lucas.demar...@intel.com>
ADL-N uses exactly the same display IP as ADL-P (unlike on the GT side
where they differ), so
Reviewed-by: Matt Roper <matthew.d.ro...@intel.com>
applied, thanks
Lucas De Marchi
