On Mon, May 06, 2024 at 12:42:03PM +0300, Jani Nikula wrote:
> On Fri, 03 May 2024, Ville Syrjala <ville.syrj...@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> >
> > Define the contents of VBT block 57 (Vswing PreEmphasis Table).
> >
> > The contents is highly platform specific. The columns of the
> > table corresponding to some set of PHY/etc registers. The rows
> > corresponding to all legal vswing+pre-emphasis combinations
> > (ie. should be 10 rows in each table). And each table
> > corresponds to a platform specific (mostly undocumented)
> > mapping based on link rate/eDP low-vswing/etc. parameters.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> I guess we should use this... but I'm not sure how.
Yeah. Based on he bug report there are at least some
ICL machines that need this.
My rough idea is:
1. change our buf_trans structs to match this (ie. make
everything u32 basically), and get the column->register
mapping from the Windows code to make sure the struct
members are in the correct order. Sadly none of this
is docuemnted in the VBT spec
2. also snoop the rules for selecting the correct table
from the Windows code, since that too is undocumented.
I think there is some kind of note about this for ICL
specifically, but even that might have been outdated
3. point at the correct VBT provided table rather than
an in kernel table when appropriate
But I think there are some additional complications due to
mg/dkl vs. combo PHY as well. So probably not 100% trivial.
I don't totally like step 1 of that plan as it'll increase
the size of the in kernel buf_trans tables needlessly. But
the alternative would involve converting the VBT layout
into our layout as needed, which is perhaps a bit less
straightforward. Dunno.
> Reviewed-by: Jani Nikula <jani.nik...@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 50d0d96fca67..0e5a2bf429f4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -184,6 +184,7 @@ enum bdb_block_id {
> > BDB_MIPI_SEQUENCE = 53, /* 177+ */
> > BDB_RGB_PALETTE = 54, /* 180+ */
> > BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */
> > + BDB_VSWING_PREEMPH = 57, /* 218+ */
> > BDB_GENERIC_DTD = 58, /* 229+ */
> > BDB_SKIP = 254, /* VBIOS only */
> > };
> > @@ -1486,6 +1487,16 @@ struct bdb_compression_parameters {
> > struct dsc_compression_parameters_entry data[16];
> > } __packed;
> >
> > +/*
> > + * Block 57 - Vswing PreEmphasis Table
> > + */
> > +
> > +struct bdb_vswing_preemph {
> > + u8 num_tables;
> > + u8 num_columns;
> > + u32 tables[];
> > +} __packed;
> > +
> > /*
> > * Block 58 - Generic DTD Block
> > */
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
