On Tue, May 07, 2024 at 03:56:48PM +0300, Jani Nikula wrote:
> It's confusing for INTEL_CFL_IDS() to include all CML PCI IDs. Even if
> we treat them the same in a lot of places, CML is a platform of its own,
> and the lists of PCI IDs should not conflate them.
>
> Cc: Bjorn Helgaas <bhelg...@google.com>
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Jani Nikula <jani.nik...@intel.com>
> ---
> arch/x86/kernel/early-quirks.c | 1 +
> drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
> include/drm/i915_pciids.h | 12 +++++++-----
> 3 files changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
> index 59f4aefc6bc1..2e2d15be4025 100644
> --- a/arch/x86/kernel/early-quirks.c
> +++ b/arch/x86/kernel/early-quirks.c
> @@ -547,6 +547,7 @@ static const struct pci_device_id intel_early_ids[]
> __initconst = {
> INTEL_BXT_IDS(&gen9_early_ops),
> INTEL_KBL_IDS(&gen9_early_ops),
> INTEL_CFL_IDS(&gen9_early_ops),
> + INTEL_CML_IDS(&gen9_early_ops),
> INTEL_GLK_IDS(&gen9_early_ops),
> INTEL_CNL_IDS(&gen9_early_ops),
> INTEL_ICL_11_IDS(&gen11_early_ops),
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
> b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 56a2e17d7d9e..3aa7d1cdd228 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -832,6 +832,7 @@ static const struct {
> INTEL_GLK_IDS(&glk_display),
> INTEL_KBL_IDS(&skl_display),
> INTEL_CFL_IDS(&skl_display),
> + INTEL_CML_IDS(&skl_display),
> INTEL_ICL_11_IDS(&icl_display),
> INTEL_EHL_IDS(&jsl_ehl_display),
> INTEL_JSL_IDS(&jsl_ehl_display),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index 85ce33ad6e26..5f52c504ffde 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -472,6 +472,12 @@
> INTEL_VGA_DEVICE(0x9BCA, info), \
> INTEL_VGA_DEVICE(0x9BCC, info)
>
> +#define INTEL_CML_IDS(info) \
> + INTEL_CML_GT1_IDS(info), \
> + INTEL_CML_GT2_IDS(info), \
> + INTEL_CML_U_GT1_IDS(info), \
> + INTEL_CML_U_GT2_IDS(info)
> +
> #define INTEL_KBL_IDS(info) \
> INTEL_KBL_GT1_IDS(info), \
> INTEL_KBL_GT2_IDS(info), \
> @@ -535,11 +541,7 @@
> INTEL_WHL_U_GT1_IDS(info), \
> INTEL_WHL_U_GT2_IDS(info), \
> INTEL_WHL_U_GT3_IDS(info), \
> - INTEL_AML_CFL_GT2_IDS(info), \
> - INTEL_CML_GT1_IDS(info), \
> - INTEL_CML_GT2_IDS(info), \
> - INTEL_CML_U_GT1_IDS(info), \
> - INTEL_CML_U_GT2_IDS(info)
> + INTEL_AML_CFL_GT2_IDS(info)
Why only CML and not AML and WHL as well?
>
> /* CNL */
> #define INTEL_CNL_PORT_F_IDS(info) \
> --
> 2.39.2
>
