> -----Original Message-----
> From: Hogander, Jouni <jouni.hogan...@intel.com>
> Sent: Friday, May 10, 2024 3:08 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.ma...@intel.com>; Hogander, Jouni
> <jouni.hogan...@intel.com>
> Subject: [PATCH v10 08/12] drm/i915/psr: Panel replay uses SRD_STATUS to
> track it's status
>
> DP Panel replay uses SRD_STATUS to track it's status despite selective update
> mode.
>
> Bspec: 53370, 68920
>
> v4:
> - use PSR2_STATUS for eDP Panel Replay
> - handle intel_psr_wait_exit_locked as well
> v3:
> - do not use PSR2_STATUS for PSR1
> v2:
> - use intel_dp_is_edp to differentiate
> - modify debugfs status as well
>
> Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
Reviewed-by: Animesh Manna <animesh.ma...@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 6d1f442f3d14..532a80a3eeea 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2111,7 +2111,8 @@ static void intel_psr_wait_exit_locked(struct
> intel_dp *intel_dp)
> i915_reg_t psr_status;
> u32 psr_status_mask;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -2849,6 +2850,13 @@ static int
> _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
> EDP_PSR_STATUS_STATE_MASK, 50); }
>
> +static int _panel_replay_ready_for_pipe_update_locked(struct intel_dp
> +*intel_dp) {
> + return intel_dp_is_edp(intel_dp) ?
> + _psr2_ready_for_pipe_update_locked(intel_dp) :
> + _psr1_ready_for_pipe_update_locked(intel_dp);
> +}
> +
> /**
> * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
> * @new_crtc_state: new CRTC state
> @@ -2874,7 +2882,9 @@ void intel_psr_wait_for_idle_locked(const struct
> intel_crtc_state *new_crtc_stat
> if (!intel_dp->psr.enabled)
> continue;
>
> - if (intel_dp->psr.sel_update_enabled)
> + if (intel_dp->psr.panel_replay_enabled)
> + ret =
> _panel_replay_ready_for_pipe_update_locked(intel_dp);
> + else if (intel_dp->psr.sel_update_enabled)
> ret =
> _psr2_ready_for_pipe_update_locked(intel_dp);
> else
> ret =
> _psr1_ready_for_pipe_update_locked(intel_dp);
> @@ -2895,7 +2905,8 @@ static bool __psr_wait_for_idle_locked(struct
> intel_dp *intel_dp)
> if (!intel_dp->psr.enabled)
> return false;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder);
> mask = EDP_PSR2_STATUS_STATE_MASK;
> } else {
> @@ -3517,7 +3528,8 @@ psr_source_status(struct intel_dp *intel_dp, struct
> seq_file *m)
> const char *status = "unknown";
> u32 val, status_val;
>
> - if (intel_dp->psr.sel_update_enabled) {
> + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled
> ||
> + intel_dp-
> >psr.panel_replay_enabled)) {
> static const char * const live_status[] = {
> "IDLE",
> "CAPTURE",
> --
> 2.34.1
