Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the CURPOS register macro.
Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++---
4 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index 573bbdec3e3d..17039d37dc91 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -298,14 +298,14 @@ static void i845_cursor_update_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base);
intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
- intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl);
plane->cursor.base = base;
plane->cursor.size = size;
plane->cursor.cntl = cntl;
} else {
- intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos);
}
}
@@ -647,14 +647,14 @@ static void i9xx_cursor_update_arm(struct intel_plane
*plane,
intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
fbc_ctl);
intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl);
- intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
plane->cursor.base = base;
plane->cursor.size = fbc_ctl;
plane->cursor.cntl = cntl;
} else {
- intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
+ intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 4a7e27f0c3c1..d0fa251ae8c4 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -68,7 +68,7 @@
#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
-#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
+#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c
b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 60f368affb6c..e78de423a6c7 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -384,7 +384,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
return -EINVAL;
}
- val = vgpu_vreg_t(vgpu, CURPOS(pipe));
+ val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe));
plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index f562172995a6..5ea1fbc2e981 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -148,9 +148,9 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(CURCNTR(dev_priv, PIPE_A));
MMIO_D(CURCNTR(dev_priv, PIPE_B));
MMIO_D(CURCNTR(dev_priv, PIPE_C));
- MMIO_D(CURPOS(PIPE_A));
- MMIO_D(CURPOS(PIPE_B));
- MMIO_D(CURPOS(PIPE_C));
+ MMIO_D(CURPOS(dev_priv, PIPE_A));
+ MMIO_D(CURPOS(dev_priv, PIPE_B));
+ MMIO_D(CURPOS(dev_priv, PIPE_C));
MMIO_D(CURBASE(dev_priv, PIPE_A));
MMIO_D(CURBASE(dev_priv, PIPE_B));
MMIO_D(CURBASE(dev_priv, PIPE_C));
--
2.39.2
