[PATCH v2 2/3] drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide

[Jouni Högander]

On LunarLake  PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this
into account when enabling PSR2_CTL.

Bspec: 69885

Signed-off-by: Jouni Högander <jouni.hogan...@intel.com>
Reviewed-by: Uma Shankar <uma.shan...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c      | 2 ++
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c 
b/drivers/gpu/drm/i915/display/intel_psr.c
index f5d3eb776833..d2f6488b8fc7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -958,6 +958,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 
                tmp = map[psr->alpm_parameters.fast_wake_lines - 
TGL_EDP_PSR2_FAST_WAKE_MIN_LINES];
                val |= TGL_EDP_PSR2_FAST_WAKE(tmp + 
TGL_EDP_PSR2_FAST_WAKE_MIN_LINES);
+       } else if (DISPLAY_VER(dev_priv) >= 20) {
+               val |= 
LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
        } else if (DISPLAY_VER(dev_priv) >= 12) {
                val |= 
TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines);
                val |= 
TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines);
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h 
b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index e14cb48f2614..b6a39926ccb6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -172,6 +172,10 @@
 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES        5
 #define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)   
REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
                                                               (lines) - 
TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
+#define   LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK     REG_GENMASK(18, 13)
+#define   LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES        5
+#define   LNL_EDP_PSR2_IO_BUFFER_WAKE(lines)   
REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \
+                                                              (lines) - 
LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES)
 #define   EDP_PSR2_FAST_WAKE_MASK              REG_GENMASK(12, 11)
 #define   EDP_PSR2_FAST_WAKE_MAX_LINES         8
 #define   EDP_PSR2_FAST_WAKE(lines)            
REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \
-- 
2.34.1