[PATCH 07/16] drm/i915: pass dev_priv explicitly to DSPSIZE

[Jani Nikula]

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPSIZE register macro.

Signed-off-by: Jani Nikula <jani.nik...@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c      | 2 +-
 drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +-
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c    | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c 
b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b23135ed1a38..42175cb74d5d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -439,7 +439,7 @@ static void i9xx_plane_update_noarm(struct intel_plane 
*plane,
                 */
                intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane),
                                  DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
-               intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
+               intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane),
                                  DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 
1));
        }
 }
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h 
b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 13a49550c456..5a1f45eceed4 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -60,7 +60,7 @@
 #define   DISP_POS_X(x)                        REG_FIELD_PREP(DISP_POS_X_MASK, 
(x))
 
 #define _DSPASIZE                              0x70190 /* pre-g4x */
-#define DSPSIZE(plane)                         _MMIO_PIPE2(dev_priv, plane, 
_DSPASIZE)
+#define DSPSIZE(dev_priv, plane)               _MMIO_PIPE2(dev_priv, plane, 
_DSPASIZE)
 #define   DISP_HEIGHT_MASK             REG_GENMASK(31, 16)
 #define   DISP_HEIGHT(h)               REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
 #define   DISP_WIDTH_MASK              REG_GENMASK(15, 0)
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c 
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 00dd2b647c83..e047928c3ea0 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -169,7 +169,7 @@ static int iterate_generic_mmio(struct 
intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPADDR(dev_priv, PIPE_A));
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_A));
        MMIO_D(DSPPOS(dev_priv, PIPE_A));
-       MMIO_D(DSPSIZE(PIPE_A));
+       MMIO_D(DSPSIZE(dev_priv, PIPE_A));
        MMIO_D(DSPSURF(PIPE_A));
        MMIO_D(DSPOFFSET(PIPE_A));
        MMIO_D(DSPSURFLIVE(PIPE_A));
@@ -178,7 +178,7 @@ static int iterate_generic_mmio(struct 
intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPADDR(dev_priv, PIPE_B));
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_B));
        MMIO_D(DSPPOS(dev_priv, PIPE_B));
-       MMIO_D(DSPSIZE(PIPE_B));
+       MMIO_D(DSPSIZE(dev_priv, PIPE_B));
        MMIO_D(DSPSURF(PIPE_B));
        MMIO_D(DSPOFFSET(PIPE_B));
        MMIO_D(DSPSURFLIVE(PIPE_B));
@@ -187,7 +187,7 @@ static int iterate_generic_mmio(struct 
intel_gvt_mmio_table_iter *iter)
        MMIO_D(DSPADDR(dev_priv, PIPE_C));
        MMIO_D(DSPSTRIDE(dev_priv, PIPE_C));
        MMIO_D(DSPPOS(dev_priv, PIPE_C));
-       MMIO_D(DSPSIZE(PIPE_C));
+       MMIO_D(DSPSIZE(dev_priv, PIPE_C));
        MMIO_D(DSPSURF(PIPE_C));
        MMIO_D(DSPOFFSET(PIPE_C));
        MMIO_D(DSPSURFLIVE(PIPE_C));
-- 
2.39.2