== Series Details ==
Series: Implement CMRR Support (rev11)
URL : https://patchwork.freedesktop.org/series/126443/
State : warning
== Summary ==
Error: dim checkpatch failed
d5bd8c92e48d drm/i915: Separate VRR related register definitions
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 226 lines checked
a339c7372329 drm/i915: Define and compute Transcoder CMRR registers
-:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible
side-effects?
#57: FILE: drivers/gpu/drm/i915/display/intel_display.c:5064:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
-:57: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as
'(name)' to avoid precedence issues
#57: FILE: drivers/gpu/drm/i915/display/intel_display.c:5064:
+#define PIPE_CONF_CHECK_LLI(name) do { \
+ if (current_config->name != pipe_config->name) { \
+ pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+ "(expected %lli, found %lli)", \
+ current_config->name, \
+ pipe_config->name); \
+ ret = false; \
+ } \
+} while (0)
total: 0 errors, 0 warnings, 2 checks, 114 lines checked
f520cbe47de3 drm/i915: Update trans_vrr_ctl flag when cmrr is computed
a580d500d303 drm/dp: Add refresh rate divider to struct representing AS SDP
b235aefbbea5 drm/i915/display: Add support for pack and unpack
f9f8ba96c798 drm/i915/display: Compute Adaptive sync SDP params
179d89423fe3 drm/i915/display: Compute vrr vsync params
f2a7dddb6b92 drm/i915: Compute CMRR and calculate vtotal
