[PATCH 1/1] drm/i915/display: On Xe2 platform always require ccs alignment on tile4

[Juha-Pekka Heikkila]

On Xe2 platform with tile4 decompression is enabled unconditionally
hence consider tile4 as ccs modifier

Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikk...@gmail.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c 
b/drivers/gpu/drm/i915/display/intel_fb.c
index f23547a88b1f..c36d5a9dc5ac 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1733,7 +1733,8 @@ intel_fb_stride_alignment(const struct drm_framebuffer 
*fb, int color_plane)
        }
 
        tile_width = intel_tile_width_bytes(fb, color_plane);
-       if (intel_fb_is_ccs_modifier(fb->modifier)) {
+       if (intel_fb_is_ccs_modifier(fb->modifier) ||
+           (GRAPHICS_VER(dev_priv) >= 20 && fb->modifier == 
I915_FORMAT_MOD_4_TILED)) {
                /*
                 * On TGL the surface stride must be 4 tile aligned, mapped by
                 * one 64 byte cacheline on the CCS AUX surface.
-- 
2.43.2