[RFC PATCH v2 01/11] drm/i915/gt: Move the CCS mode variable to a global position

[Andi Shyti]

Store the CCS mode value in the intel_gt->ccs structure to make
it available for future instances that may need to change its
value.

Name it mode_reg_val because it holds the value that will
be written into the CCS_MODE register, determining the CCS
balancing and, consequently, the number of engines generated.

Create a mutex to control access to the mode_reg_val variable.

No functional changes intended.

Signed-off-by: Andi Shyti <andi.sh...@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c          |  3 +++
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 13 ++++++++++---
 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h |  3 ++-
 drivers/gpu/drm/i915/gt/intel_gt_types.h    | 12 ++++++++++++
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  7 ++++---
 5 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index a6c69a706fd7..5af0527d822d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -18,6 +18,7 @@
 #include "intel_ggtt_gmch.h"
 #include "intel_gt.h"
 #include "intel_gt_buffer_pool.h"
+#include "intel_gt_ccs_mode.h"
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_debugfs.h"
 #include "intel_gt_mcr.h"
@@ -136,6 +137,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
        intel_sseu_info_init(gt);
        intel_gt_mcr_init(gt);
 
+       intel_gt_ccs_mode_init(gt);
+
        return intel_engines_init_mmio(gt);
 }
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c 
b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 3c62a44e9106..19e0bc359861 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
@@ -8,14 +8,16 @@
 #include "intel_gt_ccs_mode.h"
 #include "intel_gt_regs.h"
 
-unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
+void intel_gt_apply_ccs_mode(struct intel_gt *gt)
 {
        int cslice;
        u32 mode = 0;
        int first_ccs = __ffs(CCS_MASK(gt));
 
+       lockdep_assert_held(&gt->ccs.mutex);
+
        if (!IS_DG2(gt->i915))
-               return 0;
+               return;
 
        /* Build the value for the fixed CCS load balancing */
        for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
@@ -35,5 +37,10 @@ unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt)
                                                     XEHP_CCS_MODE_CSLICE_MASK);
        }
 
-       return mode;
+       gt->ccs.mode_reg_val = mode;
+}
+
+void intel_gt_ccs_mode_init(struct intel_gt *gt)
+{
+       mutex_init(&gt->ccs.mutex);
 }
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h 
b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
index 55547f2ff426..e646ab595ded 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.h
@@ -8,6 +8,7 @@
 
 struct intel_gt;
 
-unsigned int intel_gt_apply_ccs_mode(struct intel_gt *gt);
+void intel_gt_apply_ccs_mode(struct intel_gt *gt);
+void intel_gt_ccs_mode_init(struct intel_gt *gt);
 
 #endif /* __INTEL_GT_CCS_MODE_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h 
b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index bcee084b1f27..8df8fac066c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -207,12 +207,24 @@ struct intel_gt {
                                            [MAX_ENGINE_INSTANCE + 1];
        enum intel_submission_method submission_method;
 
+       /*
+        * Track fixed mapping between CCS engines and compute slices.
+        *
+        * In order to w/a HW that has the inability to dynamically load
+        * balance between CCS engines and EU in the compute slices, we have to
+        * reconfigure a static mapping on the fly.
+        *
+        * The mode variable is set by the user and sets the balancing mode,
+        * i.e. how the CCS streams are distributed amongs the slices.
+        */
        struct {
                /*
                 * Mask of the non fused CCS slices
                 * to be used for the load balancing
                 */
                intel_engine_mask_t cslices;
+               struct mutex mutex;
+               u32 mode_reg_val;
        } ccs;
 
        /*
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c 
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index bfe6d8fc820f..daa11e11d68f 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2727,7 +2727,6 @@ add_render_compute_tuning_settings(struct intel_gt *gt,
 static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct 
i915_wa_list *wal)
 {
        struct intel_gt *gt = engine->gt;
-       u32 mode;
 
        if (!IS_DG2(gt->i915))
                return;
@@ -2744,8 +2743,10 @@ static void ccs_engine_wa_mode(struct intel_engine_cs 
*engine, struct i915_wa_li
         * After having disabled automatic load balancing we need to
         * assign all slices to a single CCS. We will call it CCS mode 1
         */
-       mode = intel_gt_apply_ccs_mode(gt);
-       wa_masked_en(wal, XEHP_CCS_MODE, mode);
+       mutex_lock(&gt->ccs.mutex);
+       intel_gt_apply_ccs_mode(gt);
+       wa_masked_en(wal, XEHP_CCS_MODE, gt->ccs.mode_reg_val);
+       mutex_unlock(&gt->ccs.mutex);
 }
 
 /*
-- 
2.45.2